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\c CMPNEQPS xmm1,xmm2/mem128 ; 0F C2 /r 04 [KATMAI,SSE]
\c CMPNLTPS xmm1,xmm2/mem128 ; 0F C2 /r 05 [KATMAI,SSE]
\c CMPNLEPS xmm1,xmm2/mem128 ; 0F C2 /r 06 [KATMAI,SSE]
\c CMPORDPS xmm1,xmm2/mem128 ; 0F C2 /r 07 [KATMAI,SSE]
The \c{CMPccPS} instructions compare the two packed single-precision
FP values in the source and destination operands, and returns the
result of the comparison in the destination register. The result of
each comparison is a doubleword mask of all 1s (comparison true) or
all 0s (comparison false).
The destination is an \c{XMM} register. The source can be either an
\c{XMM} register or a 128-bit memory location.
The third operand is an 8-bit immediate value, of which the low 3
bits define the type of comparison. For ease of programming, the
8 two-operand pseudo-instructions are provided, with the third
operand already filled in. The \I{Condition Predicates}
\c{Condition Predicates} are:
\c EQ 0 Equal
\c LT 1 Less-than
\c LE 2 Less-than-or-equal
\c UNORD 3 Unordered
\c NE 4 Not-equal
\c NLT 5 Not-less-than
\c NLE 6 Not-less-than-or-equal
\c ORD 7 Ordered
For more details of the comparison predicates, and details of how
to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
\S{insCMPSB} \i\c{CMPSB}, \i\c{CMPSW}, \i\c{CMPSD}: Compare Strings
\c CMPSB ; A6 [8086]
\c CMPSW ; o16 A7 [8086]
\c CMPSD ; o32 A7 [386]
\c{CMPSB} compares the byte at \c{[DS:SI]} or \c{[DS:ESI]} with the
byte at \c{[ES:DI]} or \c{[ES:EDI]}, and sets the flags accordingly.
It then increments or decrements (depending on the direction flag:
increments if the flag is clear, decrements if it is set) \c{SI} and
\c{DI} (or \c{ESI} and \c{EDI}).
The registers used are \c{SI} and \c{DI} if the address size is 16
bits, and \c{ESI} and \c{EDI} if it is 32 bits. If you need to use
an address size not equal to the current \c{BITS} setting, you can
use an explicit \i\c{a16} or \i\c{a32} prefix.
The segment register used to load from \c{[SI]} or \c{[ESI]} can be
overridden by using a segment register name as a prefix (for
example, \c{ES CMPSB}). The use of \c{ES} for the load from \c{[DI]}
or \c{[EDI]} cannot be overridden.
\c{CMPSW} and \c{CMPSD} work in the same way, but they compare a
word or a doubleword instead of a byte, and increment or decrement
the addressing registers by 2 or 4 instead of 1.
The \c{REPE} and \c{REPNE} prefixes (equivalently, \c{REPZ} and
\c{REPNZ}) may be used to repeat the instruction up to \c{CX} (or
\c{ECX} - again, the address size chooses which) times until the
first unequal or equal byte is found.
\S{insCMPccSD} \i\c{CMPccSD}: Scalar Double-Precision FP Compare
\I\c{CMPEQSD} \I\c{CMPLTSD} \I\c{CMPLESD} \I\c{CMPUNORDSD}
\I\c{CMPNEQSD} \I\c{CMPNLTSD} \I\c{CMPNLESD} \I\c{CMPORDSD}
\c CMPSD xmm1,xmm2/mem64,imm8 ; F2 0F C2 /r ib [WILLAMETTE,SSE2]
\c CMPEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 00 [WILLAMETTE,SSE2]
\c CMPLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 01 [WILLAMETTE,SSE2]
\c CMPLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 02 [WILLAMETTE,SSE2]
\c CMPUNORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 03 [WILLAMETTE,SSE2]
\c CMPNEQSD xmm1,xmm2/mem64 ; F2 0F C2 /r 04 [WILLAMETTE,SSE2]
\c CMPNLTSD xmm1,xmm2/mem64 ; F2 0F C2 /r 05 [WILLAMETTE,SSE2]
\c CMPNLESD xmm1,xmm2/mem64 ; F2 0F C2 /r 06 [WILLAMETTE,SSE2]
\c CMPORDSD xmm1,xmm2/mem64 ; F2 0F C2 /r 07 [WILLAMETTE,SSE2]
The \c{CMPccSD} instructions compare the low-order double-precision
FP values in the source and destination operands, and returns the
result of the comparison in the destination register. The result of
each comparison is a quadword mask of all 1s (comparison true) or
all 0s (comparison false).
The destination is an \c{XMM} register. The source can be either an
\c{XMM} register or a 128-bit memory location.
The third operand is an 8-bit immediate value, of which the low 3
bits define the type of comparison. For ease of programming, the
8 two-operand pseudo-instructions are provided, with the third
operand already filled in. The \I{Condition Predicates}
\c{Condition Predicates} are:
\c EQ 0 Equal
\c LT 1 Less-than
\c LE 2 Less-than-or-equal
\c UNORD 3 Unordered
\c NE 4 Not-equal
\c NLT 5 Not-less-than
\c NLE 6 Not-less-than-or-equal
\c ORD 7 Ordered
For more details of the comparison predicates, and details of how
to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
\S{insCMPccSS} \i\c{CMPccSS}: Scalar Single-Precision FP Compare
\I\c{CMPEQSS} \I\c{CMPLTSS} \I\c{CMPLESS} \I\c{CMPUNORDSS}
\I\c{CMPNEQSS} \I\c{CMPNLTSS} \I\c{CMPNLESS} \I\c{CMPORDSS}
\c CMPSS xmm1,xmm2/mem32,imm8 ; F3 0F C2 /r ib [KATMAI,SSE]
\c CMPEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 00 [KATMAI,SSE]
\c CMPLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 01 [KATMAI,SSE]
\c CMPLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 02 [KATMAI,SSE]
\c CMPUNORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 03 [KATMAI,SSE]
\c CMPNEQSS xmm1,xmm2/mem32 ; F3 0F C2 /r 04 [KATMAI,SSE]
\c CMPNLTSS xmm1,xmm2/mem32 ; F3 0F C2 /r 05 [KATMAI,SSE]
\c CMPNLESS xmm1,xmm2/mem32 ; F3 0F C2 /r 06 [KATMAI,SSE]
\c CMPORDSS xmm1,xmm2/mem32 ; F3 0F C2 /r 07 [KATMAI,SSE]
The \c{CMPccSS} instructions compare the low-order single-precision
FP values in the source and destination operands, and returns the
result of the comparison in the destination register. The result of
each comparison is a doubleword mask of all 1s (comparison true) or
all 0s (comparison false).
The destination is an \c{XMM} register. The source can be either an
\c{XMM} register or a 128-bit memory location.
The third operand is an 8-bit immediate value, of which the low 3
bits define the type of comparison. For ease of programming, the
8 two-operand pseudo-instructions are provided, with the third
operand already filled in. The \I{Condition Predicates}
\c{Condition Predicates} are:
\c EQ 0 Equal
\c LT 1 Less-than
\c LE 2 Less-than-or-equal
\c UNORD 3 Unordered
\c NE 4 Not-equal
\c NLT 5 Not-less-than
\c NLE 6 Not-less-than-or-equal
\c ORD 7 Ordered
For more details of the comparison predicates, and details of how
to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}
\S{insCMPXCHG} \i\c{CMPXCHG}, \i\c{CMPXCHG486}: Compare and Exchange
\c CMPXCHG r/m8,reg8 ; 0F B0 /r [PENT]
\c CMPXCHG r/m16,reg16 ; o16 0F B1 /r [PENT]
\c CMPXCHG r/m32,reg32 ; o32 0F B1 /r [PENT]
\c CMPXCHG486 r/m8,reg8 ; 0F A6 /r [486,UNDOC]
\c CMPXCHG486 r/m16,reg16 ; o16 0F A7 /r [486,UNDOC]
\c CMPXCHG486 r/m32,reg32 ; o32 0F A7 /r [486,UNDOC]
These two instructions perform exactly the same operation; however,
apparently some (not all) 486 processors support it under a
non-standard opcode, so NASM provides the undocumented
\c{CMPXCHG486} form to generate the non-standard opcode.
\c{CMPXCHG} compares its destination (first) operand to the value in
\c{AL}, \c{AX} or \c{EAX} (depending on the operand size of the
instruction). If they are equal, it copies its source (second)
operand into the destination and sets the zero flag. Otherwise, it
clears the zero flag and copies the destination register to AL, AX or EAX.
The destination can be either a register or a memory location. The
source is a register.
\c{CMPXCHG} is intended to be used for atomic operations in
multitasking or multiprocessor environments. To safely update a
value in shared memory, for example, you might load the value into
\c{EAX}, load the updated value into \c{EBX}, and then execute the
instruction \c{LOCK CMPXCHG [value],EBX}. If \c{value} has not
changed since being loaded, it is updated with your desired new
value, and the zero flag is set to let you know it has worked. (The
\c{LOCK} prefix prevents another processor doing anything in the
middle of this operation: it guarantees atomicity.) However, if
another processor has modified the value in between your load and
your attempted store, the store does not happen, and you are
notified of the failure by a cleared zero flag, so you can go round
and try again.
\S{insCMPXCHG8B} \i\c{CMPXCHG8B}: Compare and Exchange Eight Bytes
\c CMPXCHG8B mem ; 0F C7 /1 [PENT]
This is a larger and more unwieldy version of \c{CMPXCHG}: it
compares the 64-bit (eight-byte) value stored at \c{[mem]} with the
value in \c{EDX:EAX}. If they are equal, it sets the zero flag and
stores \c{ECX:EBX} into the memory area. If they are unequal, it
clears the zero flag and stores the memory contents into \c{EDX:EAX}.
\c{CMPXCHG8B} can be used with the \c{LOCK} prefix, to allow atomic
execution. This is useful in multi-processor and multi-tasking
environments.
\S{insCOMISD} \i\c{COMISD}: Scalar Ordered Double-Precision FP Compare and Set EFLAGS
\c COMISD xmm1,xmm2/mem64 ; 66 0F 2F /r [WILLAMETTE,SSE2]
\c{COMISD} compares the low-order double-precision FP value in the
two source operands. ZF, PF and CF are set according to the result.
OF, AF and AF are cleared. The unordered result is returned if either
source is a NaN (QNaN or SNaN).
The destination operand is an \c{XMM} register. The source can be either
an \c{XMM} register or a memory location.
The flags are set according to the following rules:
\c Result Flags Values
\c UNORDERED: ZF,PF,CF <-- 111;
\c GREATER_THAN: ZF,PF,CF <-- 000;
\c LESS_THAN: ZF,PF,CF <-- 001;
\c EQUAL: ZF,PF,CF <-- 100;
\S{insCOMISS} \i\c{COMISS}: Scalar Ordered Single-Precision FP Compare and Set EFLAGS
\c COMISS xmm1,xmm2/mem32 ; 66 0F 2F /r [KATMAI,SSE]
\c{COMISS} compares the low-order single-precision FP value in the
two source operands. ZF, PF and CF are set according to the result.
OF, AF and AF are cleared. The unordered result is returned if either
source is a NaN (QNaN or SNaN).
The destination operand is an \c{XMM} register. The source can be either
an \c{XMM} register or a memory location.
The flags are set according to the following rules:
\c Result Flags Values
\c UNORDERED: ZF,PF,CF <-- 111;
\c GREATER_THAN: ZF,PF,CF <-- 000;
\c LESS_THAN: ZF,PF,CF <-- 001;
\c EQUAL: ZF,PF,CF <-- 100;
\S{insCPUID} \i\c{CPUID}: Get CPU Identification Code
\c CPUID ; 0F A2 [PENT]
\c{CPUID} returns various information about the processor it is
being executed on. It fills the four registers \c{EAX}, \c{EBX},
\c{ECX} and \c{EDX} with information, which varies depending on the
input contents of \c{EAX}.
\c{CPUID} also acts as a barrier to serialize instruction execution:
executing the \c{CPUID} instruction guarantees that all the effects
(memory modification, flag modification, register modification) of
previous instructions have been completed before the next
instruction gets fetched.
The information returned is as follows:
\b If \c{EAX} is zero on input, \c{EAX} on output holds the maximum
acceptable input value of \c{EAX}, and \c{EBX:EDX:ECX} contain the
string \c{"GenuineIntel"} (or not, if you have a clone processor).
That is to say, \c{EBX} contains \c{"Genu"} (in NASM's own sense of
character constants, described in \k{chrconst}), \c{EDX} contains
\c{"ineI"} and \c{ECX} contains \c{"ntel"}.
\b If \c{EAX} is one on input, \c{EAX} on output contains version
information about the processor, and \c{EDX} contains a set of
feature flags, showing the presence and absence of various features.
For example, bit 8 is set if the \c{CMPXCHG8B} instruction
(\k{insCMPXCHG8B}) is supported, bit 15 is set if the conditional
move instructions (\k{insCMOVcc} and \k{insFCMOVB}) are supported,
and bit 23 is set if \c{MMX} instructions are supported.
\b If \c{EAX} is two on input, \c{EAX}, \c{EBX}, \c{ECX} and \c{EDX}
all contain information about caches and TLBs (Translation Lookahead
Buffers).
For more information on the data returned from \c{CPUID}, see the
documentation from Intel and other processor manufacturers.
\S{insCVTDQ2PD} \i\c{CVTDQ2PD}:
Packed Signed INT32 to Packed Double-Precision FP Conversion
\c CVTDQ2PD xmm1,xmm2/mem64 ; F3 0F E6 /r [WILLAMETTE,SSE2]
\c{CVTDQ2PD} converts two packed signed doublewords from the source
operand to two packed double-precision FP values in the destination
operand.
The destination operand is an \c{XMM} register. The source can be
either an \c{XMM} register or a 64-bit memory locati⌨️ 快捷键说明
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