insref.src

nasm早期的源代码,比较简单是学习汇编和编译原理的好例子

in-memory values, or is greater than or equal to the second, it
throws a \c{BR} exception. Otherwise, it does nothing.


\S{insBSF} \i\c{BSF}, \i\c{BSR}: Bit Scan

\c BSF reg16,r/m16               ; o16 0F BC /r         [386]
\c BSF reg32,r/m32               ; o32 0F BC /r         [386]

\c BSR reg16,r/m16               ; o16 0F BD /r         [386]
\c BSR reg32,r/m32               ; o32 0F BD /r         [386]

\b \c{BSF} searches for the least significant set bit in its source
(second) operand, and if it finds one, stores the index in
its destination (first) operand. If no set bit is found, the
contents of the destination operand are undefined. If the source
operand is zero, the zero flag is set.

\b \c{BSR} performs the same function, but searches from the top
instead, so it finds the most significant set bit.

Bit indices are from 0 (least significant) to 15 or 31 (most
significant). The destination operand can only be a register.
The source operand can be a register or a memory location.


\S{insBSWAP} \i\c{BSWAP}: Byte Swap

\c BSWAP reg32                   ; o32 0F C8+r          [486]

\c{BSWAP} swaps the order of the four bytes of a 32-bit register:
bits 0-7 exchange places with bits 24-31, and bits 8-15 swap with
bits 16-23. There is no explicit 16-bit equivalent: to byte-swap
\c{AX}, \c{BX}, \c{CX} or \c{DX}, \c{XCHG} can be used. When \c{BSWAP}
is used with a 16-bit register, the result is undefined.


\S{insBT} \i\c{BT}, \i\c{BTC}, \i\c{BTR}, \i\c{BTS}: Bit Test

\c BT r/m16,reg16                ; o16 0F A3 /r         [386]
\c BT r/m32,reg32                ; o32 0F A3 /r         [386]
\c BT r/m16,imm8                 ; o16 0F BA /4 ib      [386]
\c BT r/m32,imm8                 ; o32 0F BA /4 ib      [386]

\c BTC r/m16,reg16               ; o16 0F BB /r         [386]
\c BTC r/m32,reg32               ; o32 0F BB /r         [386]
\c BTC r/m16,imm8                ; o16 0F BA /7 ib      [386]
\c BTC r/m32,imm8                ; o32 0F BA /7 ib      [386]

\c BTR r/m16,reg16               ; o16 0F B3 /r         [386]
\c BTR r/m32,reg32               ; o32 0F B3 /r         [386]
\c BTR r/m16,imm8                ; o16 0F BA /6 ib      [386]
\c BTR r/m32,imm8                ; o32 0F BA /6 ib      [386]

\c BTS r/m16,reg16               ; o16 0F AB /r         [386]
\c BTS r/m32,reg32               ; o32 0F AB /r         [386]
\c BTS r/m16,imm                 ; o16 0F BA /5 ib      [386]
\c BTS r/m32,imm                 ; o32 0F BA /5 ib      [386]

These instructions all test one bit of their first operand, whose
index is given by the second operand, and store the value of that
bit into the carry flag. Bit indices are from 0 (least significant)
to 15 or 31 (most significant).

In addition to storing the original value of the bit into the carry
flag, \c{BTR} also resets (clears) the bit in the operand itself.
\c{BTS} sets the bit, and \c{BTC} complements the bit. \c{BT} does
not modify its operands.

The destination can be a register or a memory location. The source can
be a register or an immediate value.

If the destination operand is a register, the bit offset should be
in the range 0-15 (for 16-bit operands) or 0-31 (for 32-bit operands).
An immediate value outside these ranges will be taken modulo 16/32
by the processor.

If the destination operand is a memory location, then an immediate
bit offset follows the same rules as for a register. If the bit offset
is in a register, then it can be anything within the signed range of
the register used (ie, for a 32-bit operand, it can be (-2^31) to (2^31 - 1)


\S{insCALL} \i\c{CALL}: Call Subroutine

\c CALL imm                      ; E8 rw/rd             [8086]
\c CALL imm:imm16                ; o16 9A iw iw         [8086]
\c CALL imm:imm32                ; o32 9A id iw         [386]
\c CALL FAR mem16                ; o16 FF /3            [8086]
\c CALL FAR mem32                ; o32 FF /3            [386]
\c CALL r/m16                    ; o16 FF /2            [8086]
\c CALL r/m32                    ; o32 FF /2            [386]

\c{CALL} calls a subroutine, by means of pushing the current
instruction pointer (\c{IP}) and optionally \c{CS} as well on the
stack, and then jumping to a given address.

\c{CS} is pushed as well as \c{IP} if and only if the call is a far
call, i.e. a destination segment address is specified in the
instruction. The forms involving two colon-separated arguments are
far calls; so are the \c{CALL FAR mem} forms.

The immediate \i{near call} takes one of two forms (\c{call imm16/imm32},
determined by the current segment size limit. For 16-bit operands,
you would use \c{CALL 0x1234}, and for 32-bit operands you would use
\c{CALL 0x12345678}. The value passed as an operand is a relative offset.

You can choose between the two immediate \i{far call} forms
(\c{CALL imm:imm}) by the use of the \c{WORD} and \c{DWORD} keywords:
\c{CALL WORD 0x1234:0x5678}) or \c{CALL DWORD 0x1234:0x56789abc}.

The \c{CALL FAR mem} forms execute a far call by loading the
destination address out of memory. The address loaded consists of 16
or 32 bits of offset (depending on the operand size), and 16 bits of
segment. The operand size may be overridden using \c{CALL WORD FAR
mem} or \c{CALL DWORD FAR mem}.

The \c{CALL r/m} forms execute a \i{near call} (within the same
segment), loading the destination address out of memory or out of a
register. The keyword \c{NEAR} may be specified, for clarity, in
these forms, but is not necessary. Again, operand size can be
overridden using \c{CALL WORD mem} or \c{CALL DWORD mem}.

As a convenience, NASM does not require you to call a far procedure
symbol by coding the cumbersome \c{CALL SEG routine:routine}, but
instead allows the easier synonym \c{CALL FAR routine}.

The \c{CALL r/m} forms given above are near calls; NASM will accept
the \c{NEAR} keyword (e.g. \c{CALL NEAR [address]}), even though it
is not strictly necessary.


\S{insCBW} \i\c{CBW}, \i\c{CWD}, \i\c{CDQ}, \i\c{CWDE}: Sign Extensions

\c CBW                           ; o16 98               [8086]
\c CWDE                          ; o32 98               [386]

\c CWD                           ; o16 99               [8086]
\c CDQ                           ; o32 99               [386]

All these instructions sign-extend a short value into a longer one,
by replicating the top bit of the original value to fill the
extended one.

\c{CBW} extends \c{AL} into \c{AX} by repeating the top bit of
\c{AL} in every bit of \c{AH}. \c{CWDE} extends \c{AX} into
\c{EAX}. \c{CWD} extends \c{AX} into \c{DX:AX} by repeating
the top bit of \c{AX} throughout \c{DX}, and \c{CDQ} extends
\c{EAX} into \c{EDX:EAX}.


\S{insCLC} \i\c{CLC}, \i\c{CLD}, \i\c{CLI}, \i\c{CLTS}: Clear Flags

\c CLC                           ; F8                   [8086]
\c CLD                           ; FC                   [8086]
\c CLI                           ; FA                   [8086]
\c CLTS                          ; 0F 06                [286,PRIV]

These instructions clear various flags. \c{CLC} clears the carry
flag; \c{CLD} clears the direction flag; \c{CLI} clears the
interrupt flag (thus disabling interrupts); and \c{CLTS} clears the
task-switched (\c{TS}) flag in \c{CR0}.

To set the carry, direction, or interrupt flags, use the \c{STC},
\c{STD} and \c{STI} instructions (\k{insSTC}). To invert the carry
flag, use \c{CMC} (\k{insCMC}).


\S{insCLFLUSH} \i\c{CLFLUSH}: Flush Cache Line

\c CLFLUSH mem                   ; 0F AE /7        [WILLAMETTE,SSE2]

\c{CLFLUSH} invalidates the cache line that contains the linear address
specified by the source operand from all levels of the processor cache
hierarchy (data and instruction). If, at any level of the cache
hierarchy, the line is inconsistent with memory (dirty) it is written
to memory before invalidation. The source operand points to a
byte-sized memory location.

Although \c{CLFLUSH} is flagged \c{SSE2} and above, it may not be
present on all processors which have \c{SSE2} support, and it may be
supported on other processors; the \c{CPUID} instruction (\k{insCPUID})
will return a bit which indicates support for the \c{CLFLUSH} instruction.


\S{insCMC} \i\c{CMC}: Complement Carry Flag

\c CMC                           ; F5                   [8086]

\c{CMC} changes the value of the carry flag: if it was 0, it sets it
to 1, and vice versa.


\S{insCMOVcc} \i\c{CMOVcc}: Conditional Move

\c CMOVcc reg16,r/m16            ; o16 0F 40+cc /r      [P6]
\c CMOVcc reg32,r/m32            ; o32 0F 40+cc /r      [P6]

\c{CMOV} moves its source (second) operand into its destination
(first) operand if the given condition code is satisfied; otherwise
it does nothing.

For a list of condition codes, see \k{iref-cc}.

Although the \c{CMOV} instructions are flagged \c{P6} and above, they
may not be supported by all Pentium Pro processors; the \c{CPUID}
instruction (\k{insCPUID}) will return a bit which indicates whether
conditional moves are supported.


\S{insCMP} \i\c{CMP}: Compare Integers

\c CMP r/m8,reg8                 ; 38 /r                [8086]
\c CMP r/m16,reg16               ; o16 39 /r            [8086]
\c CMP r/m32,reg32               ; o32 39 /r            [386]

\c CMP reg8,r/m8                 ; 3A /r                [8086]
\c CMP reg16,r/m16               ; o16 3B /r            [8086]
\c CMP reg32,r/m32               ; o32 3B /r            [386]

\c CMP r/m8,imm8                 ; 80 /7 ib             [8086]
\c CMP r/m16,imm16               ; o16 81 /7 iw         [8086]
\c CMP r/m32,imm32               ; o32 81 /7 id         [386]

\c CMP r/m16,imm8                ; o16 83 /7 ib         [8086]
\c CMP r/m32,imm8                ; o32 83 /7 ib         [386]

\c CMP AL,imm8                   ; 3C ib                [8086]
\c CMP AX,imm16                  ; o16 3D iw            [8086]
\c CMP EAX,imm32                 ; o32 3D id            [386]

\c{CMP} performs a `mental' subtraction of its second operand from
its first operand, and affects the flags as if the subtraction had
taken place, but does not store the result of the subtraction
anywhere.

In the forms with an 8-bit immediate second operand and a longer
first operand, the second operand is considered to be signed, and is
sign-extended to the length of the first operand. In these cases,
the \c{BYTE} qualifier is necessary to force NASM to generate this
form of the instruction.

The destination operand can be a register or a memory location. The
source can be a register, memory location or an immediate value of
the same size as the destination.


\S{insCMPccPD} \i\c{CMPccPD}: Packed Double-Precision FP Compare
\I\c{CMPEQPD} \I\c{CMPLTPD} \I\c{CMPLEPD} \I\c{CMPUNORDPD}
\I\c{CMPNEQPD} \I\c{CMPNLTPD} \I\c{CMPNLEPD} \I\c{CMPORDPD}

\c CMPPD xmm1,xmm2/mem128,imm8   ; 66 0F C2 /r ib  [WILLAMETTE,SSE2]

\c CMPEQPD xmm1,xmm2/mem128      ; 66 0F C2 /r 00  [WILLAMETTE,SSE2]
\c CMPLTPD xmm1,xmm2/mem128      ; 66 0F C2 /r 01  [WILLAMETTE,SSE2]
\c CMPLEPD xmm1,xmm2/mem128      ; 66 0F C2 /r 02  [WILLAMETTE,SSE2]
\c CMPUNORDPD xmm1,xmm2/mem128   ; 66 0F C2 /r 03  [WILLAMETTE,SSE2]
\c CMPNEQPD xmm1,xmm2/mem128     ; 66 0F C2 /r 04  [WILLAMETTE,SSE2]
\c CMPNLTPD xmm1,xmm2/mem128     ; 66 0F C2 /r 05  [WILLAMETTE,SSE2]
\c CMPNLEPD xmm1,xmm2/mem128     ; 66 0F C2 /r 06  [WILLAMETTE,SSE2]
\c CMPORDPD xmm1,xmm2/mem128     ; 66 0F C2 /r 07  [WILLAMETTE,SSE2]

The \c{CMPccPD} instructions compare the two packed double-precision
FP values in the source and destination operands, and returns the
result of the comparison in the destination register. The result of
each comparison is a quadword mask of all 1s (comparison true) or
all 0s (comparison false).

The destination is an \c{XMM} register. The source can be either an
\c{XMM} register or a 128-bit memory location.

The third operand is an 8-bit immediate value, of which the low 3
bits define the type of comparison. For ease of programming, the
8 two-operand pseudo-instructions are provided, with the third
operand already filled in. The \I{Condition Predicates}
\c{Condition Predicates} are:

\c EQ     0   Equal
\c LT     1   Less-than
\c LE     2   Less-than-or-equal
\c UNORD  3   Unordered
\c NE     4   Not-equal
\c NLT    5   Not-less-than
\c NLE    6   Not-less-than-or-equal
\c ORD    7   Ordered

For more details of the comparison predicates, and details of how
to emulate the "greater-than" equivalents, see \k{iref-SSE-cc}


\S{insCMPccPS} \i\c{CMPccPS}: Packed Single-Precision FP Compare
\I\c{CMPEQPS} \I\c{CMPLTPS} \I\c{CMPLEPS} \I\c{CMPUNORDPS}
\I\c{CMPNEQPS} \I\c{CMPNLTPS} \I\c{CMPNLEPS} \I\c{CMPORDPS}

\c CMPPS xmm1,xmm2/mem128,imm8   ; 0F C2 /r ib     [KATMAI,SSE]

\c CMPEQPS xmm1,xmm2/mem128      ; 0F C2 /r 00     [KATMAI,SSE]
\c CMPLTPS xmm1,xmm2/mem128      ; 0F C2 /r 01     [KATMAI,SSE]
\c CMPLEPS xmm1,xmm2/mem128      ; 0F C2 /r 02     [KATMAI,SSE]
\c CMPUNORDPS xmm1,xmm2/mem128   ; 0F C2 /r 03     [KATMAI,SSE]