📄 insref.src
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translate to and from \c{ASCII}, hence the instruction names) form.
There are also packed BCD instructions \c{DAA} and \c{DAS}: see
\k{insDAA}.
\b \c{AAA} (ASCII Adjust After Addition) should be used after a
one-byte \c{ADD} instruction whose destination was the \c{AL}
register: by means of examining the value in the low nibble of
\c{AL} and also the auxiliary carry flag \c{AF}, it determines
whether the addition has overflowed, and adjusts it (and sets
the carry flag) if so. You can add long BCD strings together
by doing \c{ADD}/\c{AAA} on the low digits, then doing
\c{ADC}/\c{AAA} on each subsequent digit.
\b \c{AAS} (ASCII Adjust AL After Subtraction) works similarly to
\c{AAA}, but is for use after \c{SUB} instructions rather than
\c{ADD}.
\b \c{AAM} (ASCII Adjust AX After Multiply) is for use after you
have multiplied two decimal digits together and left the result
in \c{AL}: it divides \c{AL} by ten and stores the quotient in
\c{AH}, leaving the remainder in \c{AL}. The divisor 10 can be
changed by specifying an operand to the instruction: a particularly
handy use of this is \c{AAM 16}, causing the two nibbles in \c{AL}
to be separated into \c{AH} and \c{AL}.
\b \c{AAD} (ASCII Adjust AX Before Division) performs the inverse
operation to \c{AAM}: it multiplies \c{AH} by ten, adds it to
\c{AL}, and sets \c{AH} to zero. Again, the multiplier 10 can
be changed.
\S{insADC} \i\c{ADC}: Add with Carry
\c ADC r/m8,reg8 ; 10 /r [8086]
\c ADC r/m16,reg16 ; o16 11 /r [8086]
\c ADC r/m32,reg32 ; o32 11 /r [386]
\c ADC reg8,r/m8 ; 12 /r [8086]
\c ADC reg16,r/m16 ; o16 13 /r [8086]
\c ADC reg32,r/m32 ; o32 13 /r [386]
\c ADC r/m8,imm8 ; 80 /2 ib [8086]
\c ADC r/m16,imm16 ; o16 81 /2 iw [8086]
\c ADC r/m32,imm32 ; o32 81 /2 id [386]
\c ADC r/m16,imm8 ; o16 83 /2 ib [8086]
\c ADC r/m32,imm8 ; o32 83 /2 ib [386]
\c ADC AL,imm8 ; 14 ib [8086]
\c ADC AX,imm16 ; o16 15 iw [8086]
\c ADC EAX,imm32 ; o32 15 id [386]
\c{ADC} performs integer addition: it adds its two operands
together, plus the value of the carry flag, and leaves the result in
its destination (first) operand. The destination operand can be a
register or a memory location. The source operand can be a register,
a memory location or an immediate value.
The flags are set according to the result of the operation: in
particular, the carry flag is affected and can be used by a
subsequent \c{ADC} instruction.
In the forms with an 8-bit immediate second operand and a longer
first operand, the second operand is considered to be signed, and is
sign-extended to the length of the first operand. In these cases,
the \c{BYTE} qualifier is necessary to force NASM to generate this
form of the instruction.
To add two numbers without also adding the contents of the carry
flag, use \c{ADD} (\k{insADD}).
\S{insADD} \i\c{ADD}: Add Integers
\c ADD r/m8,reg8 ; 00 /r [8086]
\c ADD r/m16,reg16 ; o16 01 /r [8086]
\c ADD r/m32,reg32 ; o32 01 /r [386]
\c ADD reg8,r/m8 ; 02 /r [8086]
\c ADD reg16,r/m16 ; o16 03 /r [8086]
\c ADD reg32,r/m32 ; o32 03 /r [386]
\c ADD r/m8,imm8 ; 80 /7 ib [8086]
\c ADD r/m16,imm16 ; o16 81 /7 iw [8086]
\c ADD r/m32,imm32 ; o32 81 /7 id [386]
\c ADD r/m16,imm8 ; o16 83 /7 ib [8086]
\c ADD r/m32,imm8 ; o32 83 /7 ib [386]
\c ADD AL,imm8 ; 04 ib [8086]
\c ADD AX,imm16 ; o16 05 iw [8086]
\c ADD EAX,imm32 ; o32 05 id [386]
\c{ADD} performs integer addition: it adds its two operands
together, and leaves the result in its destination (first) operand.
The destination operand can be a register or a memory location.
The source operand can be a register, a memory location or an
immediate value.
The flags are set according to the result of the operation: in
particular, the carry flag is affected and can be used by a
subsequent \c{ADC} instruction.
In the forms with an 8-bit immediate second operand and a longer
first operand, the second operand is considered to be signed, and is
sign-extended to the length of the first operand. In these cases,
the \c{BYTE} qualifier is necessary to force NASM to generate this
form of the instruction.
\S{insADDPD} \i\c{ADDPD}: ADD Packed Double-Precision FP Values
\c ADDPD xmm1,xmm2/mem128 ; 66 0F 58 /r [WILLAMETTE,SSE2]
\c{ADDPD} performs addition on each of two packed double-precision
FP value pairs.
\c dst[0-63] := dst[0-63] + src[0-63],
\c dst[64-127] := dst[64-127] + src[64-127].
The destination is an \c{XMM} register. The source operand can be
either an \c{XMM} register or a 128-bit memory location.
\S{insADDPS} \i\c{ADDPS}: ADD Packed Single-Precision FP Values
\c ADDPS xmm1,xmm2/mem128 ; 0F 58 /r [KATMAI,SSE]
\c{ADDPS} performs addition on each of four packed single-precision
FP value pairs
\c dst[0-31] := dst[0-31] + src[0-31],
\c dst[32-63] := dst[32-63] + src[32-63],
\c dst[64-95] := dst[64-95] + src[64-95],
\c dst[96-127] := dst[96-127] + src[96-127].
The destination is an \c{XMM} register. The source operand can be
either an \c{XMM} register or a 128-bit memory location.
\S{insADDSD} \i\c{ADDSD}: ADD Scalar Double-Precision FP Values
\c ADDSD xmm1,xmm2/mem64 ; F2 0F 58 /r [KATMAI,SSE]
\c{ADDSD} adds the low double-precision FP values from the source
and destination operands and stores the double-precision FP result
in the destination operand.
\c dst[0-63] := dst[0-63] + src[0-63],
\c dst[64-127) remains unchanged.
The destination is an \c{XMM} register. The source operand can be
either an \c{XMM} register or a 64-bit memory location.
\S{insADDSS} \i\c{ADDSS}: ADD Scalar Single-Precision FP Values
\c ADDSS xmm1,xmm2/mem32 ; F3 0F 58 /r [WILLAMETTE,SSE2]
\c{ADDSS} adds the low single-precision FP values from the source
and destination operands and stores the single-precision FP result
in the destination operand.
\c dst[0-31] := dst[0-31] + src[0-31],
\c dst[32-127] remains unchanged.
The destination is an \c{XMM} register. The source operand can be
either an \c{XMM} register or a 32-bit memory location.
\S{insAND} \i\c{AND}: Bitwise AND
\c AND r/m8,reg8 ; 20 /r [8086]
\c AND r/m16,reg16 ; o16 21 /r [8086]
\c AND r/m32,reg32 ; o32 21 /r [386]
\c AND reg8,r/m8 ; 22 /r [8086]
\c AND reg16,r/m16 ; o16 23 /r [8086]
\c AND reg32,r/m32 ; o32 23 /r [386]
\c AND r/m8,imm8 ; 80 /4 ib [8086]
\c AND r/m16,imm16 ; o16 81 /4 iw [8086]
\c AND r/m32,imm32 ; o32 81 /4 id [386]
\c AND r/m16,imm8 ; o16 83 /4 ib [8086]
\c AND r/m32,imm8 ; o32 83 /4 ib [386]
\c AND AL,imm8 ; 24 ib [8086]
\c AND AX,imm16 ; o16 25 iw [8086]
\c AND EAX,imm32 ; o32 25 id [386]
\c{AND} performs a bitwise AND operation between its two operands
(i.e. each bit of the result is 1 if and only if the corresponding
bits of the two inputs were both 1), and stores the result in the
destination (first) operand. The destination operand can be a
register or a memory location. The source operand can be a register,
a memory location or an immediate value.
In the forms with an 8-bit immediate second operand and a longer
first operand, the second operand is considered to be signed, and is
sign-extended to the length of the first operand. In these cases,
the \c{BYTE} qualifier is necessary to force NASM to generate this
form of the instruction.
The \c{MMX} instruction \c{PAND} (see \k{insPAND}) performs the same
operation on the 64-bit \c{MMX} registers.
\S{insANDNPD} \i\c{ANDNPD}: Bitwise Logical AND NOT of
Packed Double-Precision FP Values
\c ANDNPD xmm1,xmm2/mem128 ; 66 0F 55 /r [WILLAMETTE,SSE2]
\c{ANDNPD} inverts the bits of the two double-precision
floating-point values in the destination register, and then
performs a logical AND between the two double-precision
floating-point values in the source operand and the temporary
inverted result, storing the result in the destination register.
\c dst[0-63] := src[0-63] AND NOT dst[0-63],
\c dst[64-127] := src[64-127] AND NOT dst[64-127].
The destination is an \c{XMM} register. The source operand can be
either an \c{XMM} register or a 128-bit memory location.
\S{insANDNPS} \i\c{ANDNPS}: Bitwise Logical AND NOT of
Packed Single-Precision FP Values
\c ANDNPS xmm1,xmm2/mem128 ; 0F 55 /r [KATMAI,SSE]
\c{ANDNPS} inverts the bits of the four single-precision
floating-point values in the destination register, and then
performs a logical AND between the four single-precision
floating-point values in the source operand and the temporary
inverted result, storing the result in the destination register.
\c dst[0-31] := src[0-31] AND NOT dst[0-31],
\c dst[32-63] := src[32-63] AND NOT dst[32-63],
\c dst[64-95] := src[64-95] AND NOT dst[64-95],
\c dst[96-127] := src[96-127] AND NOT dst[96-127].
The destination is an \c{XMM} register. The source operand can be
either an \c{XMM} register or a 128-bit memory location.
\S{insANDPD} \i\c{ANDPD}: Bitwise Logical AND For Single FP
\c ANDPD xmm1,xmm2/mem128 ; 66 0F 54 /r [WILLAMETTE,SSE2]
\c{ANDPD} performs a bitwise logical AND of the two double-precision
floating point values in the source and destination operand, and
stores the result in the destination register.
\c dst[0-63] := src[0-63] AND dst[0-63],
\c dst[64-127] := src[64-127] AND dst[64-127].
The destination is an \c{XMM} register. The source operand can be
either an \c{XMM} register or a 128-bit memory location.
\S{insANDPS} \i\c{ANDPS}: Bitwise Logical AND For Single FP
\c ANDPS xmm1,xmm2/mem128 ; 0F 54 /r [KATMAI,SSE]
\c{ANDPS} performs a bitwise logical AND of the four single-precision
floating point values in the source and destination operand, and
stores the result in the destination register.
\c dst[0-31] := src[0-31] AND dst[0-31],
\c dst[32-63] := src[32-63] AND dst[32-63],
\c dst[64-95] := src[64-95] AND dst[64-95],
\c dst[96-127] := src[96-127] AND dst[96-127].
The destination is an \c{XMM} register. The source operand can be
either an \c{XMM} register or a 128-bit memory location.
\S{insARPL} \i\c{ARPL}: Adjust RPL Field of Selector
\c ARPL r/m16,reg16 ; 63 /r [286,PRIV]
\c{ARPL} expects its two word operands to be segment selectors. It
adjusts the \i\c{RPL} (requested privilege level - stored in the bottom
two bits of the selector) field of the destination (first) operand
to ensure that it is no less (i.e. no more privileged than) the \c{RPL}
field of the source operand. The zero flag is set if and only if a
change had to be made.
\S{insBOUND} \i\c{BOUND}: Check Array Index against Bounds
\c BOUND reg16,mem ; o16 62 /r [186]
\c BOUND reg32,mem ; o32 62 /r [386]
\c{BOUND} expects its second operand to point to an area of memory
containing two signed values of the same size as its first operand
(i.e. two words for the 16-bit form; two doublewords for the 32-bit
form). It performs two signed comparisons: if the value in the
register passed as its first operand is less than the first of the
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