insref.src

nasm早期的源代码,比较简单是学习汇编和编译原理的好例子

\c
\c NEQ    100B   not-equal   A != B                   True      No
\c
\c NLT    101B   not-less-   NOT(A < B)               True      Yes
\c               than
\c
\c NLE    110B   not-less-   NOT(A <= B)              True      Yes
\c               than-or-
\c               equal
\c
\c ---    ----   not-greater NOT(A > B)        Swap   True      Yes
\c               than                          Operands,
\c                                             Use NLT
\c
\c ---    ----   not-greater NOT(A >= B)       Swap   True      Yes
\c               than-                         Operands,
\c               or-equal                      Use NLE
\c
\c ORD    111B   ordered      A , B = Ordered         False     No

The unordered relationship is true when at least one of the two
values being compared is a NaN or in an unsupported format.

Note that the comparisons which are listed as not having a predicate
or encoding can only be achieved through software emulation, as
described in the "emulation" column. Note in particular that an
instruction such as \c{greater-than} is not the same as \c{NLE}, as,
unlike with the \c{CMP} instruction, it has to take into account the
possibility of one operand containing a NaN or an unsupported numeric
format.


\S{iref-Flags} \i{Status Flags}

The status flags provide some information about the result of the
arithmetic instructions. This information can be used by conditional
instructions (such a \c{Jcc} and \c{CMOVcc}) as well as by some of
the other instructions (such as \c{ADC} and \c{INTO}).

There are 6 status flags:

\c CF - Carry flag.

Set if an arithmetic operation generates a
carry or a borrow out of the most-significant bit of the result;
cleared otherwise. This flag indicates an overflow condition for
unsigned-integer arithmetic. It is also used in multiple-precision
arithmetic.

\c PF - Parity flag.

Set if the least-significant byte of the result contains an even
number of 1 bits; cleared otherwise.

\c AF - Adjust flag.

Set if an arithmetic operation generates a carry or a borrow
out of bit 3 of the result; cleared otherwise. This flag is used
in binary-coded decimal (BCD) arithmetic.

\c ZF - Zero flag.

Set if the result is zero; cleared otherwise.

\c SF - Sign flag.

Set equal to the most-significant bit of the result, which is the
sign bit of a signed integer. (0 indicates a positive value and 1
indicates a negative value.)

\c OF - Overflow flag.

Set if the integer result is too large a positive number or too
small a negative number (excluding the sign-bit) to fit in the
destination operand; cleared otherwise. This flag indicates an
overflow condition for signed-integer (two's complement) arithmetic.


\S{iref-ea} Effective Address Encoding: \i{ModR/M} and \i{SIB}

An \i{effective address} is encoded in up to three parts: a ModR/M
byte, an optional SIB byte, and an optional byte, word or doubleword
displacement field.

The ModR/M byte consists of three fields: the \c{mod} field, ranging
from 0 to 3, in the upper two bits of the byte, the \c{r/m} field,
ranging from 0 to 7, in the lower three bits, and the spare
(register) field in the middle (bit 3 to bit 5). The spare field is
not relevant to the effective address being encoded, and either
contains an extension to the instruction opcode or the register
value of another operand.

The ModR/M system can be used to encode a direct register reference
rather than a memory access. This is always done by setting the
\c{mod} field to 3 and the \c{r/m} field to the register value of
the register in question (it must be a general-purpose register, and
the size of the register must already be implicit in the encoding of
the rest of the instruction). In this case, the SIB byte and
displacement field are both absent.

In 16-bit addressing mode (either \c{BITS 16} with no \c{67} prefix,
or \c{BITS 32} with a \c{67} prefix), the SIB byte is never used.
The general rules for \c{mod} and \c{r/m} (there is an exception,
given below) are:

\b The \c{mod} field gives the length of the displacement field: 0
means no displacement, 1 means one byte, and 2 means two bytes.

\b The \c{r/m} field encodes the combination of registers to be
added to the displacement to give the accessed address: 0 means
\c{BX+SI}, 1 means \c{BX+DI}, 2 means \c{BP+SI}, 3 means \c{BP+DI},
4 means \c{SI} only, 5 means \c{DI} only, 6 means \c{BP} only, and 7
means \c{BX} only.

However, there is a special case:

\b If \c{mod} is 0 and \c{r/m} is 6, the effective address encoded
is not \c{[BP]} as the above rules would suggest, but instead
\c{[disp16]}: the displacement field is present and is two bytes
long, and no registers are added to the displacement.

Therefore the effective address \c{[BP]} cannot be encoded as
efficiently as \c{[BX]}; so if you code \c{[BP]} in a program, NASM
adds a notional 8-bit zero displacement, and sets \c{mod} to 1,
\c{r/m} to 6, and the one-byte displacement field to 0.

In 32-bit addressing mode (either \c{BITS 16} with a \c{67} prefix,
or \c{BITS 32} with no \c{67} prefix) the general rules (again,
there are exceptions) for \c{mod} and \c{r/m} are:

\b The \c{mod} field gives the length of the displacement field: 0
means no displacement, 1 means one byte, and 2 means four bytes.

\b If only one register is to be added to the displacement, and it
is not \c{ESP}, the \c{r/m} field gives its register value, and the
SIB byte is absent. If the \c{r/m} field is 4 (which would encode
\c{ESP}), the SIB byte is present and gives the combination and
scaling of registers to be added to the displacement.

If the SIB byte is present, it describes the combination of
registers (an optional base register, and an optional index register
scaled by multiplication by 1, 2, 4 or 8) to be added to the
displacement. The SIB byte is divided into the \c{scale} field, in
the top two bits, the \c{index} field in the next three, and the
\c{base} field in the bottom three. The general rules are:

\b The \c{base} field encodes the register value of the base
register.

\b The \c{index} field encodes the register value of the index
register, unless it is 4, in which case no index register is used
(so \c{ESP} cannot be used as an index register).

\b The \c{scale} field encodes the multiplier by which the index
register is scaled before adding it to the base and displacement: 0
encodes a multiplier of 1, 1 encodes 2, 2 encodes 4 and 3 encodes 8.

The exceptions to the 32-bit encoding rules are:

\b If \c{mod} is 0 and \c{r/m} is 5, the effective address encoded
is not \c{[EBP]} as the above rules would suggest, but instead
\c{[disp32]}: the displacement field is present and is four bytes
long, and no registers are added to the displacement.

\b If \c{mod} is 0, \c{r/m} is 4 (meaning the SIB byte is present)
and \c{base} is 5, the effective address encoded is not
\c{[EBP+index]} as the above rules would suggest, but instead
\c{[disp32+index]}: the displacement field is present and is four
bytes long, and there is no base register (but the index register is
still processed in the normal way).


\S{iref-rex} Register Extensions: The \i{REX} Prefix

The Register Extensions, or \i{REX} for short, prefix is the means
of accessing extended registers on the x86-64 architecture. \i{REX}
is considered an instruction prefix, but is required to be after
all other prefixes and thus immediately before the first instruction
opcode itself. So overall, \i{REX} can be thought of as an "Opcode
Prefix" instead. The \i{REX} prefix itself is indicated by a value
of 0x4X, where X is one of 16 different combinations of the actual
\i{REX} flags.

The \i{REX} prefix flags consist of four 1-bit extensions fields.
These flags are found in the lower nibble of the actual \i{REX}
prefix opcode. Below is the list of \i{REX} prefix flags, from
high bit to low bit.

\c{REX.W}: When set, this flag indicates the use of a 64-bit operand,
as opposed to the default of using 32-bit operands as found in 32-bit
Protected Mode.

\c{REX.R}: When set, this flag extends the \c{reg (spare)} field of
the \c{ModRM} byte. Overall, this raises the amount of addressable
registers in this field from 8 to 16.

\c{REX.X}: When set, this flag extends the \c{index} field of the
\c{SIB} byte. Overall, this raises the amount of addressable
registers in this field from 8 to 16.

\c{REX.B}: When set, this flag extends the \c{r/m} field of the
\c{ModRM} byte. This flag can also represent an extension to the
opcode register \c{(/r)} field. The determination of which is used
varies depending on which instruction is used. Overall, this raises
the amount of addressable registers in these fields from 8 to 16.

Interal use of the \i{REX} prefix by the processor is consistent,
yet non-trivial. Most instructions use the \i{REX} prefix as
indicated by the above flags. Some instructions require the \i{REX}
prefix to be present even if the flags are empty. Some instructions
default to a 64-bit operand and require the \i{REX} prefix only for
actual register extensions, and thus ignores the \c{REX.W} field
completely.

At any rate, NASM is designed to handle, and fully supports, the
\i{REX} prefix internally. Please read the appropriate processor
documentation for further information on the \i{REX} prefix.

You may have noticed that opcodes 0x40 through 0x4F are actually
opcodes for the INC/DEC instructions for each General Purpose
Register. This is, of course, correct... for legacy x86. While
in long mode, opcodes 0x40 through 0x4F are reserved for use as
the REX prefix. The other opcode forms of the INC/DEC instructions
are used instead.


\H{iref-flg} Key to Instruction Flags

Given along with each instruction in this appendix is a set of
flags, denoting the type of the instruction. The types are as follows:

\b \c{8086}, \c{186}, \c{286}, \c{386}, \c{486}, \c{PENT} and \c{P6}
denote the lowest processor type that supports the instruction. Most
instructions run on all processors above the given type; those that
do not are documented. The Pentium II contains no additional
instructions beyond the P6 (Pentium Pro); from the point of view of
its instruction set, it can be thought of as a P6 with MMX
capability.

\b \c{3DNOW} indicates that the instruction is a 3DNow! one, and will
run on the AMD K6-2 and later processors. ATHLON extensions to the
3DNow! instruction set are documented as such.

\b \c{CYRIX} indicates that the instruction is specific to Cyrix
processors, for example the extra MMX instructions in the Cyrix
extended MMX instruction set.

\b \c{FPU} indicates that the instruction is a floating-point one,
and will only run on machines with a coprocessor (automatically
including 486DX, Pentium and above).

\b \c{KATMAI} indicates that the instruction was introduced as part
of the Katmai New Instruction set. These instructions are available
on the Pentium III and later processors. Those which are not
specifically SSE instructions are also available on the AMD Athlon.

\b \c{MMX} indicates that the instruction is an MMX one, and will
run on MMX-capable Pentium processors and the Pentium II.

\b \c{PRIV} indicates that the instruction is a protected-mode
management instruction. Many of these may only be used in protected
mode, or only at privilege level zero.

\b \c{SSE} and \c{SSE2} indicate that the instruction is a Streaming
SIMD Extension instruction. These instructions operate on multiple
values in a single operation. SSE was introduced with the Pentium III
and SSE2 was introduced with the Pentium 4.

\b \c{UNDOC} indicates that the instruction is an undocumented one,
and not part of the official Intel Architecture; it may or may not
be supported on any given machine.

\b \c{WILLAMETTE} indicates that the instruction was introduced as
part of the new instruction set in the Pentium 4 and Intel Xeon
processors. These instructions are also known as SSE2 instructions.

\b \c{X64} indicates that the instruction was introduced as part of
the new instruction set in the x86-64 architecture extension,
commonly referred to as x64, AMD64 or EM64T.


\H{iref-inst} x86 Instruction Set


\S{insAAA} \i\c{AAA}, \i\c{AAS}, \i\c{AAM}, \i\c{AAD}: ASCII
Adjustments

\c AAA                           ; 37                   [8086]

\c AAS                           ; 3F                   [8086]

\c AAD                           ; D5 0A                [8086]
\c AAD imm                       ; D5 ib                [8086]

\c AAM                           ; D4 0A                [8086]
\c AAM imm                       ; D4 ib                [8086]

These instructions are used in conjunction with the add, subtract,
multiply and divide instructions to perform binary-coded decimal
arithmetic in \e{unpacked} (one BCD digit per byte - easy to