insref.src

nasm早期的源代码,比较简单是学习汇编和编译原理的好例子

\A{iref} x86 Instruction Reference

This appendix provides a complete list of the machine instructions
which NASM will assemble, and a short description of the function of
each one.

It is not intended to be an exhaustive documentation on the fine
details of the instructions' function, such as which exceptions they
can trigger: for such documentation, you should go to Intel's Web
site, \W{http://developer.intel.com/design/Pentium4/manuals/}\c{http://developer.intel.com/design/Pentium4/manuals/}.

Instead, this appendix is intended primarily to provide
documentation on the way the instructions may be used within NASM.
For example, looking up \c{LOOP} will tell you that NASM allows
\c{CX} or \c{ECX} to be specified as an optional second argument to
the \c{LOOP} instruction, to enforce which of the two possible
counter registers should be used if the default is not the one
desired.

The instructions are not quite listed in alphabetical order, since
groups of instructions with similar functions are lumped together in
the same entry. Most of them don't move very far from their
alphabetic position because of this.


\H{iref-opr} Key to Operand Specifications

The instruction descriptions in this appendix specify their operands
using the following notation:

\b Registers: \c{reg8} denotes an 8-bit \i{general purpose
register}, \c{reg16} denotes a 16-bit general purpose register,
\c{reg32} a 32-bit one and \c{reg64} a 64-bit one. \c{fpureg} denotes
one of the eight FPU stack registers, \c{mmxreg} denotes one of the
eight 64-bit MMX registers, and \c{segreg} denotes a segment register.
\c{xmmreg} denotes one of the 8, or 16 in x64 long mode, SSE XMM registers.
In addition, some registers (such as \c{AL}, \c{DX}, \c{ECX} or \c{RAX})
may be specified explicitly.

\b Immediate operands: \c{imm} denotes a generic \i{immediate operand}.
\c{imm8}, \c{imm16} and \c{imm32} are used when the operand is
intended to be a specific size. For some of these instructions, NASM
needs an explicit specifier: for example, \c{ADD ESP,16} could be
interpreted as either \c{ADD r/m32,imm32} or \c{ADD r/m32,imm8}.
NASM chooses the former by default, and so you must specify \c{ADD
ESP,BYTE 16} for the latter. There is a special case of the allowance
of an \c{imm64} for particular x64 versions of the MOV instruction.

\b Memory references: \c{mem} denotes a generic \i{memory reference};
\c{mem8}, \c{mem16}, \c{mem32}, \c{mem64} and \c{mem80} are used
when the operand needs to be a specific size. Again, a specifier is
needed in some cases: \c{DEC [address]} is ambiguous and will be
rejected by NASM. You must specify \c{DEC BYTE [address]}, \c{DEC
WORD [address]} or \c{DEC DWORD [address]} instead.

\b \i{Restricted memory references}: one form of the \c{MOV}
instruction allows a memory address to be specified \e{without}
allowing the normal range of register combinations and effective
address processing. This is denoted by \c{memoffs8}, \c{memoffs16},
\c{memoffs32} or \c{memoffs64}.

\b Register or memory choices: many instructions can accept either a
register \e{or} a memory reference as an operand. \c{r/m8} is
shorthand for \c{reg8/mem8}; similarly \c{r/m16} and \c{r/m32}.
On legacy x86 modes, \c{r/m64} is MMX-related, and is shorthand for
\c{mmxreg/mem64}. When utilizing the x86-64 architecture extension,
\c{r/m64} denotes use of a 64-bit GPR as well, and is shorthand for
\c{reg64/mem64}.


\H{iref-opc} Key to Opcode Descriptions

This appendix also provides the opcodes which NASM will generate for
each form of each instruction. The opcodes are listed in the
following way:

\b A hex number, such as \c{3F}, indicates a fixed byte containing
that number.

\b A hex number followed by \c{+r}, such as \c{C8+r}, indicates that
one of the operands to the instruction is a register, and the
`register value' of that register should be added to the hex number
to produce the generated byte. For example, EDX has register value
2, so the code \c{C8+r}, when the register operand is EDX, generates
the hex byte \c{CA}. Register values for specific registers are
given in \k{iref-rv}.

\b A hex number followed by \c{+cc}, such as \c{40+cc}, indicates
that the instruction name has a condition code suffix, and the
numeric representation of the condition code should be added to the
hex number to produce the generated byte. For example, the code
\c{40+cc}, when the instruction contains the \c{NE} condition,
generates the hex byte \c{45}. Condition codes and their numeric
representations are given in \k{iref-cc}.

\b A slash followed by a digit, such as \c{/2}, indicates that one
of the operands to the instruction is a memory address or register
(denoted \c{mem} or \c{r/m}, with an optional size). This is to be
encoded as an effective address, with a \i{ModR/M byte}, an optional
\i{SIB byte}, and an optional displacement, and the spare (register)
field of the ModR/M byte should be the digit given (which will be
from 0 to 7, so it fits in three bits). The encoding of effective
addresses is given in \k{iref-ea}.

\b The code \c{/r} combines the above two: it indicates that one of
the operands is a memory address or \c{r/m}, and another is a
register, and that an effective address should be generated with the
spare (register) field in the ModR/M byte being equal to the
`register value' of the register operand. The encoding of effective
addresses is given in \k{iref-ea}; register values are given in
\k{iref-rv}.

\b The codes \c{ib}, \c{iw} and \c{id} indicate that one of the
operands to the instruction is an immediate value, and that this is
to be encoded as a byte, little-endian word or little-endian
doubleword respectively.

\b The codes \c{rb}, \c{rw} and \c{rd} indicate that one of the
operands to the instruction is an immediate value, and that the
\e{difference} between this value and the address of the end of the
instruction is to be encoded as a byte, word or doubleword
respectively. Where the form \c{rw/rd} appears, it indicates that
either \c{rw} or \c{rd} should be used according to whether assembly
is being performed in \c{BITS 16} or \c{BITS 32} state respectively.

\b The codes \c{ow} and \c{od} indicate that one of the operands to
the instruction is a reference to the contents of a memory address
specified as an immediate value: this encoding is used in some forms
of the \c{MOV} instruction in place of the standard
effective-address mechanism. The displacement is encoded as a word
or doubleword. Again, \c{ow/od} denotes that \c{ow} or \c{od} should
be chosen according to the \c{BITS} setting.

\b The codes \c{o16} and \c{o32} indicate that the given form of the
instruction should be assembled with operand size 16 or 32 bits. In
other words, \c{o16} indicates a \c{66} prefix in \c{BITS 32} state,
but generates no code in \c{BITS 16} state; and \c{o32} indicates a
\c{66} prefix in \c{BITS 16} state but generates nothing in \c{BITS
32}.

\b The codes \c{a16} and \c{a32}, similarly to \c{o16} and \c{o32},
indicate the address size of the given form of the instruction.
Where this does not match the \c{BITS} setting, a \c{67} prefix is
required. Please note that \c{a16} is useless in long mode as
16-bit addressing is depreciated on the x86-64 architecture extension.


\S{iref-rv} Register Values

Where an instruction requires a register value, it is already
implicit in the encoding of the rest of the instruction what type of
register is intended: an 8-bit general-purpose register, a segment
register, a debug register, an MMX register, or whatever. Therefore
there is no problem with registers of different types sharing an
encoding value.

Please note that for the register classes listed below, the register
extensions (REX) classes require the use of the REX prefix, in which
is only available when in long mode on the x86-64 processor. This
pretty much goes for any register that has a number higher than 7.

The encodings for the various classes of register are:

\b 8-bit general registers: \c{AL} is 0, \c{CL} is 1, \c{DL} is 2,
\c{BL} is 3, \c{AH} is 4, \c{CH} is 5, \c{DH} is 6 and \c{BH} is
7. Please note that \c{AH}, \c{BH}, \c{CH} and \c{DH} are not
addressable when using the REX prefix in long mode.

\b 8-bit general register extensions (REX): \c{SPL} is 4, \c{BPL} is 5,
\c{SIL} is 6, \c{DIL} is 7, \c{R8B} is 8, \c{R9B} is 9, \c{R10B} is 10,
\c{R11B} is 11, \c{R12B} is 12, \c{R13B} is 13, \c{R14B} is 14 and
\c{R15B} is 15.

\b 16-bit general registers: \c{AX} is 0, \c{CX} is 1, \c{DX} is 2,
\c{BX} is 3, \c{SP} is 4, \c{BP} is 5, \c{SI} is 6, and \c{DI} is 7.

\b 16-bit general register extensions (REX): \c{R8W} is 8, \c{R9W} is 9,
\c{R10w} is 10, \c{R11W} is 11, \c{R12W} is 12, \c{R13W} is 13, \c{R14W}
is 14 and \c{R15W} is 15.

\b 32-bit general registers: \c{EAX} is 0, \c{ECX} is 1, \c{EDX} is
2, \c{EBX} is 3, \c{ESP} is 4, \c{EBP} is 5, \c{ESI} is 6, and
\c{EDI} is 7.

\b 32-bit general register extensions (REX): \c{R8D} is 8, \c{R9D} is 9,
\c{R10D} is 10, \c{R11D} is 11, \c{R12D} is 12, \c{R13D} is 13, \c{R14D}
is 14 and \c{R15D} is 15.

\b 64-bit general register extensions (REX): \c{RAX} is 0, \c{RCX} is 1,
\c{RDX} is 2, \c{RBX} is 3, \c{RSP} is 4, \c{RBP} is 5, \c{RSI} is 6,
\c{RDI} is 7, \c{R8} is 8, \c{R9} is 9, \c{R10} is 10, \c{R11} is 11,
\c{R12} is 12, \c{R13} is 13, \c{R14} is 14 and \c{R15} is 15.

\b \i{Segment registers}: \c{ES} is 0, \c{CS} is 1, \c{SS} is 2, \c{DS}
is 3, \c{FS} is 4, and \c{GS} is 5.

\b \I{floating-point, registers}Floating-point registers: \c{ST0}
is 0, \c{ST1} is 1, \c{ST2} is 2, \c{ST3} is 3, \c{ST4} is 4,
\c{ST5} is 5, \c{ST6} is 6, and \c{ST7} is 7.

\b 64-bit \i{MMX registers}: \c{MM0} is 0, \c{MM1} is 1, \c{MM2} is 2,
\c{MM3} is 3, \c{MM4} is 4, \c{MM5} is 5, \c{MM6} is 6, and \c{MM7}
is 7.

\b 128-bit \i{XMM (SSE) registers}: \c{XMM0} is 0, \c{XMM1} is 1,
\c{XMM2} is 2, \c{XMM3} is 3, \c{XMM4} is 4, \c{XMM5} is 5, \c{XMM6} is
6 and \c{XMM7} is 7.

\b 128-bit \i{XMM (SSE) register} extensions (REX): \c{XMM8} is 8,
\c{XMM9} is 9, \c{XMM10} is 10, \c{XMM11} is 11, \c{XMM12} is 12,
\c{XMM13} is 13, \c{XMM14} is 14 and \c{XMM15} is 15.

\b \i{Control registers}: \c{CR0} is 0, \c{CR2} is 2, \c{CR3} is 3,
and \c{CR4} is 4.

\b \i{Control register} extensions: \c{CR8} is 8.

\b \i{Debug registers}: \c{DR0} is 0, \c{DR1} is 1, \c{DR2} is 2,
\c{DR3} is 3, \c{DR6} is 6, and \c{DR7} is 7.

\b \i{Test registers}: \c{TR3} is 3, \c{TR4} is 4, \c{TR5} is 5,
\c{TR6} is 6, and \c{TR7} is 7.

(Note that wherever a register name contains a number, that number
is also the register value for that register.)


\S{iref-cc} \i{Condition Codes}

The available condition codes are given here, along with their
numeric representations as part of opcodes. Many of these condition
codes have synonyms, so several will be listed at a time.

In the following descriptions, the word `either', when applied to two
possible trigger conditions, is used to mean `either or both'. If
`either but not both' is meant, the phrase `exactly one of' is used.

\b \c{O} is 0 (trigger if the overflow flag is set); \c{NO} is 1.

\b \c{B}, \c{C} and \c{NAE} are 2 (trigger if the carry flag is
set); \c{AE}, \c{NB} and \c{NC} are 3.

\b \c{E} and \c{Z} are 4 (trigger if the zero flag is set); \c{NE}
and \c{NZ} are 5.

\b \c{BE} and \c{NA} are 6 (trigger if either of the carry or zero
flags is set); \c{A} and \c{NBE} are 7.

\b \c{S} is 8 (trigger if the sign flag is set); \c{NS} is 9.

\b \c{P} and \c{PE} are 10 (trigger if the parity flag is set);
\c{NP} and \c{PO} are 11.

\b \c{L} and \c{NGE} are 12 (trigger if exactly one of the sign and
overflow flags is set); \c{GE} and \c{NL} are 13.

\b \c{LE} and \c{NG} are 14 (trigger if either the zero flag is set,
or exactly one of the sign and overflow flags is set); \c{G} and
\c{NLE} are 15.

Note that in all cases, the sense of a condition code may be
reversed by changing the low bit of the numeric representation.

For details of when an instruction sets each of the status flags,
see the individual instruction, plus the Status Flags reference
in \k{iref-Flags}


\S{iref-SSE-cc} \i{SSE Condition Predicates}

The condition predicates for SSE comparison instructions are the
codes used as part of the opcode, to determine what form of
comparison is being carried out. In each case, the imm8 value is
the final byte of the opcode encoding, and the predicate is the
code used as part of the mnemonic for the instruction (equivalent
to the "cc" in an integer instruction that used a condition code).
The instructions that use this will give details of what the various
mnemonics are, this table is used to help you work out details of what
is happening.

\c Predi-  imm8  Description Relation where:   Emula- Result   QNaN
\c  cate  Encod-             A Is 1st Operand  tion   if NaN   Signal
\c         ing               B Is 2nd Operand         Operand  Invalid
\c
\c EQ     000B   equal       A = B                    False     No
\c
\c LT     001B   less-than   A < B                    False     Yes
\c
\c LE     010B   less-than-  A <= B                   False     Yes
\c                or-equal
\c
\c ---    ----   greater     A > B             Swap   False     Yes
\c               than                          Operands,
\c                                             Use LT
\c
\c ---    ----   greater-    A >= B            Swap   False     Yes
\c               than-or-equal                 Operands,
\c                                             Use LE
\c
\c UNORD  011B   unordered   A, B = Unordered         True      No