test_bcd.~(4).vhdtst

这是有关于二进制计数器的AD转换内容

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-- VHDL Testbench for bcd
-- 2008 12 9 21 19 51
-- Created by "EditVHDL"
-- "Copyright (c) 2002 Altium Limited"
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Library IEEE;
Use     IEEE.std_logic_1164.all;
Use     IEEE.std_logic_textio.all;
Use     STD.textio.all;
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entity Testbcd is
end Testbcd;
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architecture stimulus of Testbcd is
    file RESULTS: TEXT open WRITE_MODE is "results.txt";
    procedure WRITE_RESULTS(
    ) is
        variable l_out : line;
    begin
        write(l_out, now, right, 15);
        writeline(RESULTS, l_out);
    end procedure;

    component bcd
        port (
        );
    end component;


begin
    DUT:bcd port map (
    );

    STIMULUS0:process
    begin

        ENABLE<='1';
        CLEAR<='1';
        wait for 1ns;
        CLEAR<='0';
        wait;
    end process;
    CLK0:process
    begin
    CLOK<='1';
    wait for 10ns;
      CLOK<='0';
    wait for 10ns;
    end process;
    WRITE_RESULTS(UPPER,LOWER,URCO,PARITY
    );

end architecture;
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