iop_sw_cpu_defs_asm.h

linux内核源码

#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24
#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25
#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25
#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26
#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26
#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27
#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27
#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28
#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28
#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29
#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29
#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30
#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30
#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31
#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1
#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31
#define reg_iop_sw_cpu_r_masked_intr1_offset 112

/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15
#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16
#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16
#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17
#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29
#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30
#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30
#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31
#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1
#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31
#define reg_iop_sw_cpu_rw_intr2_mask_offset 116

/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1
#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15
#define reg_iop_sw_cpu_rw_ack_intr2_offset 120

/* Register r_intr2, scope iop_sw_cpu, type r */
#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0
#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1
#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0
#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1
#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1
#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1
#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2
#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1
#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2
#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3
#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1
#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3
#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4
#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1
#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4
#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5
#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1
#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5
#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6
#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1
#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6
#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7
#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1
#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7
#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8
#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1
#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8
#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9
#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1
#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9
#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10
#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1
#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10
#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11
#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1
#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11
#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12
#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1
#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12
#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13
#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1
#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13
#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14
#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1
#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14
#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15
#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1
#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15
#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16
#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1
#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16
#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17
#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1
#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17
#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18
#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1
#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18
#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19
#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1
#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19
#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20
#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1
#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20
#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21
#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1
#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21
#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22
#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1
#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22
#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23
#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1
#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23
#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24
#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1
#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24
#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25
#define reg_iop_sw_cpu_r_intr2