msp_regs.h

linux内核源码

/* Extended ELB addressing */
#define CS0_EXT_ADDR_REG	regptr(MSP_SLP_BASE + 0x1A0)
					/* CS0 Extended address         */
#define CS1_EXT_ADDR_REG	regptr(MSP_SLP_BASE + 0x1A4)
					/* CS1 Extended address         */
#define CS2_EXT_ADDR_REG	regptr(MSP_SLP_BASE + 0x1A8)
					/* CS2 Extended address         */
#define CS3_EXT_ADDR_REG	regptr(MSP_SLP_BASE + 0x1AC)
					/* CS3 Extended address         */
/* reserved					      0x1B0             */
#define CS5_EXT_ADDR_REG	regptr(MSP_SLP_BASE + 0x1B4)
					/* CS5 Extended address         */

/* PLL Adjustment registers */
#define PLL_LOCK_REG		regptr(MSP_SLP_BASE + 0x200)
					/* PLL0 lock status             */
#define PLL_ARST_REG		regptr(MSP_SLP_BASE + 0x204)
					/* PLL Analog reset status      */
#define PLL0_ADJ_REG		regptr(MSP_SLP_BASE + 0x208)
					/* PLL0 Adjustment value        */
#define PLL1_ADJ_REG		regptr(MSP_SLP_BASE + 0x20C)
					/* PLL1 Adjustment value        */

/*
 ***************************************************************************
 * Peripheral Register definitions                                         *
 ***************************************************************************
 */

/* Peripheral status */
#define PER_CTRL_REG		regptr(MSP_PER_BASE + 0x50)
					/* Peripheral control register  */
#define PER_STS_REG		regptr(MSP_PER_BASE + 0x54)
					/* Peripheral status register   */

/* SPI/MPI Registers */
#define SMPI_TX_SZ_REG		regptr(MSP_PER_BASE + 0x58)
					/* SPI/MPI Tx Size register     */
#define SMPI_RX_SZ_REG		regptr(MSP_PER_BASE + 0x5C)
					/* SPI/MPI Rx Size register     */
#define SMPI_CTL_REG		regptr(MSP_PER_BASE + 0x60)
					/* SPI/MPI Control register     */
#define SMPI_MS_REG		regptr(MSP_PER_BASE + 0x64)
					/* SPI/MPI Chip Select reg      */
#define SMPI_CORE_DATA_REG	regptr(MSP_PER_BASE + 0xC0)
					/* SPI/MPI Core Data reg        */
#define SMPI_CORE_CTRL_REG	regptr(MSP_PER_BASE + 0xC4)
					/* SPI/MPI Core Control reg     */
#define SMPI_CORE_STAT_REG	regptr(MSP_PER_BASE + 0xC8)
					/* SPI/MPI Core Status reg      */
#define SMPI_CORE_SSEL_REG	regptr(MSP_PER_BASE + 0xCC)
					/* SPI/MPI Core Ssel reg        */
#define SMPI_FIFO_REG		regptr(MSP_PER_BASE + 0xD0)
					/* SPI/MPI Data FIFO reg        */

/* Peripheral Block Error Registers           */
#define PER_ERR_STS_REG		regptr(MSP_PER_BASE + 0x70)
					/* Error Bit Status Register    */
#define PER_ERR_MSK_REG		regptr(MSP_PER_BASE + 0x74)
					/* Error Bit Mask Register      */
#define PER_HDR1_REG		regptr(MSP_PER_BASE + 0x78)
					/* Error Header 1 Register      */
#define PER_HDR2_REG		regptr(MSP_PER_BASE + 0x7C)
					/* Error Header 2 Register      */

/* Peripheral Block Interrupt Registers       */
#define PER_INT_STS_REG		regptr(MSP_PER_BASE + 0x80)
					/* Interrupt status register    */
#define PER_INT_MSK_REG		regptr(MSP_PER_BASE + 0x84)
					/* Interrupt Mask Register      */
#define GPIO_INT_STS_REG	regptr(MSP_PER_BASE + 0x88)
					/* GPIO interrupt status reg    */
#define GPIO_INT_MSK_REG	regptr(MSP_PER_BASE + 0x8C)
					/* GPIO interrupt MASK Reg      */

/* POLO GPIO registers                        */
#define POLO_GPIO_DAT1_REG	regptr(MSP_PER_BASE + 0x0E0)
					/* Polo GPIO[8:0]  data reg     */
#define POLO_GPIO_CFG1_REG	regptr(MSP_PER_BASE + 0x0E4)
					/* Polo GPIO[7:0]  config reg   */
#define POLO_GPIO_CFG2_REG	regptr(MSP_PER_BASE + 0x0E8)
					/* Polo GPIO[15:8] config reg   */
#define POLO_GPIO_OD1_REG	regptr(MSP_PER_BASE + 0x0EC)
					/* Polo GPIO[31:0] output drive */
#define POLO_GPIO_CFG3_REG	regptr(MSP_PER_BASE + 0x170)
					/* Polo GPIO[23:16] config reg  */
#define POLO_GPIO_DAT2_REG	regptr(MSP_PER_BASE + 0x174)
					/* Polo GPIO[15:9]  data reg    */
#define POLO_GPIO_DAT3_REG	regptr(MSP_PER_BASE + 0x178)
					/* Polo GPIO[23:16]  data reg   */
#define POLO_GPIO_DAT4_REG	regptr(MSP_PER_BASE + 0x17C)
					/* Polo GPIO[31:24]  data reg   */
#define POLO_GPIO_DAT5_REG	regptr(MSP_PER_BASE + 0x180)
					/* Polo GPIO[39:32]  data reg   */
#define POLO_GPIO_DAT6_REG	regptr(MSP_PER_BASE + 0x184)
					/* Polo GPIO[47:40]  data reg   */
#define POLO_GPIO_DAT7_REG	regptr(MSP_PER_BASE + 0x188)
					/* Polo GPIO[54:48]  data reg   */
#define POLO_GPIO_CFG4_REG	regptr(MSP_PER_BASE + 0x18C)
					/* Polo GPIO[31:24] config reg  */
#define POLO_GPIO_CFG5_REG	regptr(MSP_PER_BASE + 0x190)
					/* Polo GPIO[39:32] config reg  */
#define POLO_GPIO_CFG6_REG	regptr(MSP_PER_BASE + 0x194)
					/* Polo GPIO[47:40] config reg  */
#define POLO_GPIO_CFG7_REG	regptr(MSP_PER_BASE + 0x198)
					/* Polo GPIO[54:48] config reg  */
#define POLO_GPIO_OD2_REG	regptr(MSP_PER_BASE + 0x19C)
					/* Polo GPIO[54:32] output drive */

/* Generic GPIO registers                     */
#define GPIO_DATA1_REG		regptr(MSP_PER_BASE + 0x170)
					/* GPIO[1:0] data register      */
#define GPIO_DATA2_REG		regptr(MSP_PER_BASE + 0x174)
					/* GPIO[5:2] data register      */
#define GPIO_DATA3_REG		regptr(MSP_PER_BASE + 0x178)
					/* GPIO[9:6] data register      */
#define GPIO_DATA4_REG		regptr(MSP_PER_BASE + 0x17C)
					/* GPIO[15:10] data register    */
#define GPIO_CFG1_REG		regptr(MSP_PER_BASE + 0x180)
					/* GPIO[1:0] config register    */
#define GPIO_CFG2_REG		regptr(MSP_PER_BASE + 0x184)
					/* GPIO[5:2] config register    */
#define GPIO_CFG3_REG		regptr(MSP_PER_BASE + 0x188)
					/* GPIO[9:6] config register    */
#define GPIO_CFG4_REG		regptr(MSP_PER_BASE + 0x18C)
					/* GPIO[15:10] config register  */
#define GPIO_OD_REG		regptr(MSP_PER_BASE + 0x190)
					/* GPIO[15:0] output drive      */

/*
 ***************************************************************************
 * CPU Interface register definitions                                      *
 ***************************************************************************
 */
#define PCI_FLUSH_REG		regptr(MSP_CPUIF_BASE + 0x00)
					/* PCI-SDRAM queue flush trigger */
#define OCP_ERR1_REG		regptr(MSP_CPUIF_BASE + 0x04)
					/* OCP Error Attribute 1        */
#define OCP_ERR2_REG		regptr(MSP_CPUIF_BASE + 0x08)
					/* OCP Error Attribute 2        */
#define OCP_STS_REG		regptr(MSP_CPUIF_BASE + 0x0C)
					/* OCP Error Status             */
#define CPUIF_PM_REG		regptr(MSP_CPUIF_BASE + 0x10)
					/* CPU policy configuration     */
#define CPUIF_CFG_REG		regptr(MSP_CPUIF_BASE + 0x10)
					/* Misc configuration options   */

/* Central Interrupt Controller Registers */
#define MSP_CIC_BASE		(MSP_CPUIF_BASE + 0x8000)
					/* Central Interrupt registers  */
#define CIC_EXT_CFG_REG		regptr(MSP_CIC_BASE + 0x00)
					/* External interrupt config    */
#define CIC_STS_REG		regptr(MSP_CIC_BASE + 0x04)
					/* CIC Interrupt Status         */
#define CIC_VPE0_MSK_REG	regptr(MSP_CIC_BASE + 0x08)
					/* VPE0 Interrupt Mask          */
#define CIC_VPE1_MSK_REG	regptr(MSP_CIC_BASE + 0x0C)
					/* VPE1 Interrupt Mask          */
#define CIC_TC0_MSK_REG		regptr(MSP_CIC_BASE + 0x10)
					/* Thread Context 0 Int Mask    */
#define CIC_TC1_MSK_REG		regptr(MSP_CIC_BASE + 0x14)
					/* Thread Context 1 Int Mask    */
#define CIC_TC2_MSK_REG		regptr(MSP_CIC_BASE + 0x18)
					/* Thread Context 2 Int Mask    */
#define CIC_TC3_MSK_REG		regptr(MSP_CIC_BASE + 0x18)
					/* Thread Context 3 Int Mask    */
#define CIC_TC4_MSK_REG		regptr(MSP_CIC_BASE + 0x18)
					/* Thread Context 4 Int Mask    */
#define CIC_PCIMSI_STS_REG	regptr(MSP_CIC_BASE + 0x18)
#define CIC_PCIMSI_MSK_REG	regptr(MSP_CIC_BASE + 0x18)
#define CIC_PCIFLSH_REG		regptr(MSP_CIC_BASE + 0x18)
#define CIC_VPE0_SWINT_REG	regptr(MSP_CIC_BASE + 0x08)


/*
 ***************************************************************************
 * Memory controller registers                                             *
 ***************************************************************************
 */
#define MEM_CFG1_REG		regptr(MSP_MEM_CFG_BASE + 0x00)
#define MEM_SS_ADDR		regptr(MSP_MEM_CFG_BASE + 0x00)
#define MEM_SS_DATA		regptr(MSP_MEM_CFG_BASE + 0x04)
#define MEM_SS_WRITE		regptr(MSP_MEM_CFG_BASE + 0x08)

/*
 ***************************************************************************
 * PCI controller registers                                                *
 ***************************************************************************
 */
#define PCI_BASE_REG		regptr(MSP_PCI_BASE + 0x00)
#define PCI_CONFIG_SPACE_REG	regptr(MSP_PCI_BASE + 0x800)
#define PCI_JTAG_DEVID_REG	regptr(MSP_SLP_BASE + 0x13c)

/*
 ########################################################################
 #  Register content & macro definitions                                #
 ########################################################################
 */

/*
 ***************************************************************************
 * DEV_ID defines                                                          *
 ***************************************************************************
 */
#define DEV_ID_PCI_DIS		(1 << 26)       /* Set if PCI disabled */
#define DEV_ID_PCI_HOST		(1 << 20)       /* Set if PCI host */
#define DEV_ID_SINGLE_PC	(1 << 19)       /* Set if single PC Card */
#define DEV_ID_FAMILY		(0xff << 8)     /* family ID code */
#define POLO_ZEUS_SUB_FAMILY	(0x7  << 16)    /* sub family for Polo/Zeus */

#define MSPFPGA_ID		(0x00  << 8)    /* you are on your own here */
#define MSP5000_ID		(0x50  << 8)
#define MSP4F00_ID		(0x4f  << 8)    /* FPGA version of MSP4200 */
#define MSP4E00_ID		(0x4f  << 8)    /* FPGA version of MSP7120 */
#define MSP4200_ID		(0x42  << 8)
#define MSP4000_ID		(0x40  << 8)
#define MSP2XXX_ID		(0x20  << 8)
#define MSPZEUS_ID		(0x10  << 8)

#define MSP2004_SUB_ID		(0x0   << 16)
#define MSP2005_SUB_ID		(0x1   << 16)
#define MSP2006_SUB_ID		(0x1   << 16)
#define MSP2007_SUB_ID		(0x2   << 16)
#define MSP2010_SUB_ID		(0x3   << 16)
#define MSP2015_SUB_ID		(0x4   << 16)
#define MSP2020_SUB_ID		(0x5   << 16)
#define MSP2100_SUB_ID		(0x6   << 16)

/*
 ***************************************************************************
 * RESET defines                                                           *
 ***************************************************************************
 */
#define MSP_GR_RST		(0x01 << 0)     /* Global reset bit     */
#define MSP_MR_RST		(0x01 << 1)     /* MIPS reset bit       */
#define MSP_PD_RST		(0x01 << 2)     /* PVC DMA reset bit    */
#define MSP_PP_RST		(0x01 << 3)     /* PVC reset bit        */
/* reserved                                                             */
#define MSP_EA_RST		(0x01 << 6)     /* Mac A reset bit      */
#define MSP_EB_RST		(0x01 << 7)     /* Mac B reset bit      */
#define MSP_SE_RST		(0x01 << 8)     /* Security Eng reset bit */
#define MSP_PB_RST		(0x01 << 9)     /* Per block reset bit  */
#define MSP_EC_RST		(0x01 << 10)    /* Mac C reset bit      */
#define MSP_TW_RST		(0x01 << 11)    /* TWI reset bit        */
#define MSP_SPI_RST		(0x01 << 12)    /* SPI/MPI reset bit    */
#define MSP_U1_RST		(0x01 << 13)    /* UART1 reset bit      */
#define MSP_U0_RST		(0x01 << 14)    /* UART0 reset bit      */

/*
 ***************************************************************************
 * UART defines                                                            *
 ***************************************************************************
 */
#ifndef CONFIG_MSP_FPGA
#define MSP_BASE_BAUD		25000000
#else
#define MSP_BASE_BAUD		6000000
#endif
#define MSP_UART_REG_LEN	0x20

/*
 ***************************************************************************
 * ELB defines                                                             *
 ***************************************************************************
 */
#define PCCARD_32		0x02    /* Set if is PCCARD 32 (Cardbus) */
#define SINGLE_PCCARD		0x01    /* Set to enable single PC card */

/*
 ***************************************************************************
 * CIC defines                                                             *
 ***************************************************************************
 */

/* CIC_EXT_CFG_REG */
#define EXT_INT_POL(eirq)			(1 << (eirq + 8))
#define EXT_INT_EDGE(eirq)			(1 << eirq)

#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq)	(reg &= ~EXT_INT_EDGE(eirq))
#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq)	(reg |= EXT_INT_EDGE(eirq))
#define CIC_EXT_SET_ACTIVE_HI(reg, eirq)	(reg |= EXT_INT_POL(eirq))
#define CIC_EXT_SET_ACTIVE_LO(reg, eirq)	(reg &= ~EXT_INT_POL(eirq))
#define CIC_EXT_SET_ACTIVE_RISING		CIC_EXT_SET_ACTIVE_HI
#define CIC_EXT_SET_ACTIVE_FALLING		CIC_EXT_SET_ACTIVE_LO

#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
				((reg & EXT_INT_EDGE(eirq)) == 0)
#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq)	(reg & EXT_INT_EDGE(eirq))
#define CIC_EXT_IS_ACTIVE_HI(reg, eirq)		(reg & EXT_INT_POL(eirq))
#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
				((reg & EXT_INT_POL(eirq)) == 0)
#define CIC_EXT_IS_ACTIVE_RISING		CIC_EXT_IS_ACTIVE_HI
#define CIC_EXT_IS_ACTIVE_FALLING		CIC_EXT_IS_ACTIVE_LO

/*
 ***************************************************************************
 * Memory Controller defines                                               *
 ***************************************************************************
 */

/* Indirect memory controller registers */
#define DDRC_CFG(n)		(n)
#define DDRC_DEBUG(n)		(0x04 + n)
#define DDRC_CTL(n)		(0x40 + n)

/* Macro to perform DDRC indirect write */
#define DDRC_INDIRECT_WRITE(reg, mask, value) \
({ \
	*MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
	*MEM_SS_DATA = (value); \
	*MEM_SS_WRITE = 1; \
})

/*
 ***************************************************************************
 * SPI/MPI Mode                                                            *
 ***************************************************************************
 */
#define SPI_MPI_RX_BUSY		0x00008000	/* SPI/MPI Receive Busy */
#define SPI_MPI_FIFO_EMPTY	0x00004000	/* SPI/MPI Fifo Empty   */
#define SPI_MPI_TX_BUSY		0x00002000	/* SPI/MPI Transmit Busy */
#define SPI_MPI_FIFO_FULL	0x00001000	/* SPI/MPU FIFO full    */

/*
 ***************************************************************************
 * SPI/MPI Control Register                                                *
 ***************************************************************************
 */
#define SPI_MPI_RX_START	0x00000004	/* Start receive command */
#define SPI_MPI_FLUSH_Q		0x00000002	/* Flush SPI/MPI Queue */
#define SPI_MPI_TX_START	0x00000001	/* Start Transmit Command */

#endif /* !_ASM_MSP_REGS_H */