msp_regs.h

linux内核源码

/*
 * Defines for the address space, registers and register configuration
 * (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
 * This file contains addess maps for all the devices in the line of
 * products but only has register definitions and configuration masks for
 * registers which aren't definitely associated with any device.  Things
 * like clock settings, reset access, the ELB etc.  Individual device
 * drivers will reference the appropriate XXX_BASE value defined here
 * and have individual registers offset from that.
 *
 * Copyright (C) 2005-2007 PMC-Sierra, Inc.  All rights reserved.
 * Author: Andrew Hughes, [e-mail]
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 *
 * ########################################################################
 */

#include <asm/addrspace.h>
#include <linux/types.h>

#ifndef _ASM_MSP_REGS_H
#define _ASM_MSP_REGS_H

/*
 ########################################################################
 #  Address space and device base definitions                           #
 ########################################################################
 */

/*
 ***************************************************************************
 * System Logic and Peripherals (ELB, UART0, etc) device address space     *
 ***************************************************************************
 */
#define MSP_SLP_BASE		0x1c000000
					/* System Logic and Peripherals */
#define MSP_RST_BASE		(MSP_SLP_BASE + 0x10)
					/* System reset register base	*/
#define MSP_RST_SIZE		0x0C	/* System reset register space	*/

#define MSP_WTIMER_BASE		(MSP_SLP_BASE + 0x04C)
					/* watchdog timer base          */
#define MSP_ITIMER_BASE		(MSP_SLP_BASE + 0x054)
					/* internal timer base          */
#define MSP_UART0_BASE		(MSP_SLP_BASE + 0x100)
					/* UART0 controller base        */
#define MSP_BCPY_CTRL_BASE	(MSP_SLP_BASE + 0x120)
					/* Block Copy controller base   */
#define MSP_BCPY_DESC_BASE	(MSP_SLP_BASE + 0x160)
					/* Block Copy descriptor base   */

/*
 ***************************************************************************
 * PCI address space                                                       *
 ***************************************************************************
 */
#define MSP_PCI_BASE		0x19000000

/*
 ***************************************************************************
 * MSbus device address space                                              *
 ***************************************************************************
 */
#define MSP_MSB_BASE		0x18000000
					/* MSbus address start          */
#define MSP_PER_BASE		(MSP_MSB_BASE + 0x400000)
					/* Peripheral device registers  */
#define MSP_MAC0_BASE		(MSP_MSB_BASE + 0x600000)
					/* MAC A device registers       */
#define MSP_MAC1_BASE		(MSP_MSB_BASE + 0x700000)
					/* MAC B device registers       */
#define MSP_MAC_SIZE		0xE0	/* MAC register space		*/

#define MSP_SEC_BASE		(MSP_MSB_BASE + 0x800000)
					/* Security Engine registers    */
#define MSP_MAC2_BASE		(MSP_MSB_BASE + 0x900000)
					/* MAC C device registers       */
#define MSP_ADSL2_BASE		(MSP_MSB_BASE + 0xA80000)
					/* ADSL2 device registers       */
#define MSP_USB_BASE		(MSP_MSB_BASE + 0xB40000)
					/* USB device registers         */
#define MSP_USB_BASE_START	(MSP_MSB_BASE + 0xB40100)
					/* USB device registers         */
#define MSP_USB_BASE_END	(MSP_MSB_BASE + 0xB401FF)
					/* USB device registers         */
#define MSP_CPUIF_BASE		(MSP_MSB_BASE + 0xC00000)
					/* CPU interface registers      */

/* Devices within the MSbus peripheral block */
#define MSP_UART1_BASE		(MSP_PER_BASE + 0x030)
					/* UART1 controller base        */
#define MSP_SPI_BASE		(MSP_PER_BASE + 0x058)
					/* SPI/MPI control registers    */
#define MSP_TWI_BASE		(MSP_PER_BASE + 0x090)
					/* Two-wire control registers   */
#define MSP_PTIMER_BASE		(MSP_PER_BASE + 0x0F0)
					/* Programmable timer control   */

/*
 ***************************************************************************
 * Physical Memory configuration address space                             *
 ***************************************************************************
 */
#define MSP_MEM_CFG_BASE	0x17f00000

#define MSP_MEM_INDIRECT_CTL_10	0x10

/*
 * Notes:
 *  1) The SPI registers are split into two blocks, one offset from the
 *     MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
 *     0x68.  The SPI driver definitions for the register must be aware
 *     of this.
 *  2) The block copy engine register are divided into two regions, one
 *     for the control/configuration of the engine proper and one for the
 *     values of the descriptors used in the copy process.  These have
 *     different base defines (CTRL_BASE vs DESC_BASE)
 *  3) These constants are for physical addresses which means that they
 *     work correctly with "ioremap" and friends.  This means that device
 *     drivers will need to remap these addresses using ioremap and perhaps
 *     the readw/writew macros.  Or they could use the regptr() macro
 *     defined below, but the readw/writew calls are the correct thing.
 *  4) The UARTs have an additional status register offset from the base
 *     address.  This register isn't used in the standard 8250 driver but
 *     may be used in other software.  Consult the hardware datasheet for
 *     offset details.
 *  5) For some unknown reason the security engine (MSP_SEC_BASE) registers
 *     start at an offset of 0x84 from the base address but the block of
 *     registers before this is reserved for the security engine.  The
 *     driver will have to be aware of this but it makes the register
 *     definitions line up better with the documentation.
 */

/*
 ########################################################################
 #  System register definitions.  Not associated with a specific device #
 ########################################################################
 */

/*
 * This macro maps the physical register number into uncached space
 * and (for C code) casts it into a u32 pointer so it can be dereferenced
 * Normally these would be accessed with ioremap and readX/writeX, but
 * these are convenient for a lot of internal kernel code.
 */
#ifdef __ASSEMBLER__
	#define regptr(addr) (KSEG1ADDR(addr))
#else
	#define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
#endif

/*
 ***************************************************************************
 * System Logic and Peripherals (RESET, ELB, etc) registers                *
 ***************************************************************************
 */

/* System Control register definitions */
#define	DEV_ID_REG	regptr(MSP_SLP_BASE + 0x00)
					/* Device-ID                 RO */
#define	FWR_ID_REG	regptr(MSP_SLP_BASE + 0x04)
					/* Firmware-ID Register      RW */
#define	SYS_ID_REG0	regptr(MSP_SLP_BASE + 0x08)
					/* System-ID Register-0      RW */
#define	SYS_ID_REG1	regptr(MSP_SLP_BASE + 0x0C)
					/* System-ID Register-1      RW */

/* System Reset register definitions */
#define	RST_STS_REG	regptr(MSP_SLP_BASE + 0x10)
					/* System Reset Status       RO */
#define	RST_SET_REG	regptr(MSP_SLP_BASE + 0x14)
					/* System Set Reset          WO */
#define	RST_CLR_REG	regptr(MSP_SLP_BASE + 0x18)
					/* System Clear Reset        WO */

/* System Clock Registers */
#define PCI_SLP_REG	regptr(MSP_SLP_BASE + 0x1C)
					/* PCI clock generator       RW */
#define URT_SLP_REG	regptr(MSP_SLP_BASE + 0x20)
					/* UART clock generator      RW */
/* reserved		      (MSP_SLP_BASE + 0x24)                     */
/* reserved		      (MSP_SLP_BASE + 0x28)                     */
#define PLL1_SLP_REG	regptr(MSP_SLP_BASE + 0x2C)
					/* PLL1 clock generator      RW */
#define PLL0_SLP_REG	regptr(MSP_SLP_BASE + 0x30)
					/* PLL0 clock generator      RW */
#define MIPS_SLP_REG	regptr(MSP_SLP_BASE + 0x34)
					/* MIPS clock generator      RW */
#define	VE_SLP_REG	regptr(MSP_SLP_BASE + 0x38)
					/* Voice Eng clock generator RW */
/* reserved		      (MSP_SLP_BASE + 0x3C)                     */
#define MSB_SLP_REG	regptr(MSP_SLP_BASE + 0x40)
					/* MS-Bus clock generator    RW */
#define SMAC_SLP_REG	regptr(MSP_SLP_BASE + 0x44)
					/* Sec & MAC clock generator RW */
#define PERF_SLP_REG	regptr(MSP_SLP_BASE + 0x48)
					/* Per & TDM clock generator RW */

/* Interrupt Controller Registers */
#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
					/* Interrupt status register RW */
#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
					/* Interrupt enable/mask     RW */
#define SE_MBOX_REG	regptr(MSP_SLP_BASE + 0x78)
					/* Security Engine mailbox   RW */
#define VE_MBOX_REG	regptr(MSP_SLP_BASE + 0x7C)
					/* Voice Engine mailbox      RW */

/* ELB Controller Registers */
#define CS0_CNFG_REG	regptr(MSP_SLP_BASE + 0x80)
					/* ELB CS0 Configuration Reg    */
#define CS0_ADDR_REG	regptr(MSP_SLP_BASE + 0x84)
					/* ELB CS0 Base Address Reg     */
#define CS0_MASK_REG	regptr(MSP_SLP_BASE + 0x88)
					/* ELB CS0 Mask Register        */
#define CS0_ACCESS_REG	regptr(MSP_SLP_BASE + 0x8C)
					/* ELB CS0 access register      */

#define CS1_CNFG_REG	regptr(MSP_SLP_BASE + 0x90)
					/* ELB CS1 Configuration Reg    */
#define CS1_ADDR_REG	regptr(MSP_SLP_BASE + 0x94)
					/* ELB CS1 Base Address Reg     */
#define CS1_MASK_REG	regptr(MSP_SLP_BASE + 0x98)
					/* ELB CS1 Mask Register        */
#define CS1_ACCESS_REG	regptr(MSP_SLP_BASE + 0x9C)
					/* ELB CS1 access register      */

#define CS2_CNFG_REG	regptr(MSP_SLP_BASE + 0xA0)
					/* ELB CS2 Configuration Reg    */
#define CS2_ADDR_REG	regptr(MSP_SLP_BASE + 0xA4)
					/* ELB CS2 Base Address Reg     */
#define CS2_MASK_REG	regptr(MSP_SLP_BASE + 0xA8)
					/* ELB CS2 Mask Register        */
#define CS2_ACCESS_REG	regptr(MSP_SLP_BASE + 0xAC)
					/* ELB CS2 access register      */

#define CS3_CNFG_REG	regptr(MSP_SLP_BASE + 0xB0)
					/* ELB CS3 Configuration Reg    */
#define CS3_ADDR_REG	regptr(MSP_SLP_BASE + 0xB4)
					/* ELB CS3 Base Address Reg     */
#define CS3_MASK_REG	regptr(MSP_SLP_BASE + 0xB8)
					/* ELB CS3 Mask Register        */
#define CS3_ACCESS_REG	regptr(MSP_SLP_BASE + 0xBC)
					/* ELB CS3 access register      */

#define CS4_CNFG_REG	regptr(MSP_SLP_BASE + 0xC0)
					/* ELB CS4 Configuration Reg    */
#define CS4_ADDR_REG	regptr(MSP_SLP_BASE + 0xC4)
					/* ELB CS4 Base Address Reg     */
#define CS4_MASK_REG	regptr(MSP_SLP_BASE + 0xC8)
					/* ELB CS4 Mask Register        */
#define CS4_ACCESS_REG	regptr(MSP_SLP_BASE + 0xCC)
					/* ELB CS4 access register      */

#define CS5_CNFG_REG	regptr(MSP_SLP_BASE + 0xD0)
					/* ELB CS5 Configuration Reg    */
#define CS5_ADDR_REG	regptr(MSP_SLP_BASE + 0xD4)
					/* ELB CS5 Base Address Reg     */
#define CS5_MASK_REG	regptr(MSP_SLP_BASE + 0xD8)
					/* ELB CS5 Mask Register        */
#define CS5_ACCESS_REG	regptr(MSP_SLP_BASE + 0xDC)
					/* ELB CS5 access register      */

/* reserved			       0xE0 - 0xE8                      */
#define ELB_1PC_EN_REG	regptr(MSP_SLP_BASE + 0xEC)
					/* ELB single PC card detect    */

/* reserved			       0xF0 - 0xF8                      */
#define ELB_CLK_CFG_REG	regptr(MSP_SLP_BASE + 0xFC)
					/* SDRAM read/ELB timing Reg    */

/* Extended UART status registers */
#define UART0_STATUS_REG	regptr(MSP_UART0_BASE + 0x0c0)
					/* UART Status Register 0       */
#define UART1_STATUS_REG	regptr(MSP_UART1_BASE + 0x170)
					/* UART Status Register 1       */

/* Performance monitoring registers */
#define PERF_MON_CTRL_REG	regptr(MSP_SLP_BASE + 0x140)
					/* Performance monitor control  */
#define PERF_MON_CLR_REG	regptr(MSP_SLP_BASE + 0x144)
					/* Performance monitor clear    */
#define PERF_MON_CNTH_REG	regptr(MSP_SLP_BASE + 0x148)
					/* Perf monitor counter high    */
#define PERF_MON_CNTL_REG	regptr(MSP_SLP_BASE + 0x14C)
					/* Perf monitor counter low     */

/* System control registers */
#define SYS_CTRL_REG		regptr(MSP_SLP_BASE + 0x150)
					/* System control register      */
#define SYS_ERR1_REG		regptr(MSP_SLP_BASE + 0x154)
					/* System Error status 1        */
#define SYS_ERR2_REG		regptr(MSP_SLP_BASE + 0x158)
					/* System Error status 2        */
#define SYS_INT_CFG_REG		regptr(MSP_SLP_BASE + 0x15C)
					/* System Interrupt config      */

/* Voice Engine Memory configuration */
#define VE_MEM_REG		regptr(MSP_SLP_BASE + 0x17C)
					/* Voice engine memory config   */

/* CPU/SLP Error Status registers */
#define CPU_ERR1_REG		regptr(MSP_SLP_BASE + 0x180)
					/* CPU/SLP Error status 1       */
#define CPU_ERR2_REG		regptr(MSP_SLP_BASE + 0x184)
					/* CPU/SLP Error status 1       */

#define EXTENDED_GPIO_REG	regptr(MSP_SLP_BASE + 0x188)
					/* Extended GPIO register       */

/* System Error registers */
#define SLP_ERR_STS_REG		regptr(MSP_SLP_BASE + 0x190)
					/* Int status for SLP errors    */
#define SLP_ERR_MSK_REG		regptr(MSP_SLP_BASE + 0x194)
					/* Int mask for SLP errors      */
#define SLP_ELB_ERST_REG	regptr(MSP_SLP_BASE + 0x198)
					/* External ELB reset           */
#define SLP_BOOT_STS_REG	regptr(MSP_SLP_BASE + 0x19C)
					/* Boot Status                  */