skfbi.h

linux内核源码

#define	SM_WR_WAIT_TC4	0x6	/* Write Desc.	Wait_TC4	   Re	     */
#define	SM_WR_LD_A_T	0x6	/* Write Desc.	Load_A		Tr   	     */
#define	SM_WR_LD_A_R	0x7	/* Write Desc.	Load_A		   Re	     */
#define	SM_WR_WAIT_TC_T	0x7	/* Write Desc.	Wait_TC		Tr   	     */
#define	SM_WR_LD_N2C_T	0xc	/* Write Desc.	Load_N2C	Tr   	     */
#define	SM_WR_WDONE_T	0x9	/* Write Desc.	Wait_Done	Tr   	     */
#define	SM_WR_WDONE_R	0xc	/* Write Desc.	Wait_Done	   Re	     */
#define SM_WR_LD_D_AD	0xe	/* Write Desc.  Load_Dumr_A	   Re	(ML) */
#define SM_WR_WAIT_D_TC	0xf	/* Write Desc.	Wait_Dumr_TC	   Re	(ML) */

/*	B5_<xx>_T2	32 bit Test Register 2		 (xx) */
/* Note: This register is only defined for the transmit queues */
				/* Bit 31..8:	reserved */
#define	AC_TEST_ON	(1<<7)	/* Bit 7:	Address Counter Test Mode on */
#define	AC_TEST_OFF	(1<<6)	/* Bit 6:	Address Counter Test Mode off*/
#define	BC_TEST_ON	(1<<5)	/* Bit 5:	Byte Counter Test Mode on */
#define	BC_TEST_OFF	(1<<4)	/* Bit 4:	Byte Counter Test Mode off */
#define	TEST_STEP04	(1<<3)	/* Bit 3:	Inc AC/Dec BC by 4 */
#define	TEST_STEP03	(1<<2)	/* Bit 2:	Inc AC/Dec BC by 3 */
#define	TEST_STEP02	(1<<1)	/* Bit 1:	Inc AC/Dec BC by 2 */
#define	TEST_STEP01	(1<<0)	/* Bit 0:	Inc AC/Dec BC by 1 */

/*	B5_<xx>_T3	32 bit Test Register 3		 (xx) */
/* Note: This register is only defined for the transmit queues */
				/* Bit 31..8:	reserved */
#define T3_MUX_2	(1<<7)	/* Bit 7: (ML)	Mux position MSB */
#define T3_VRAM_2	(1<<6)	/* Bit 6: (ML)	Virtual RAM buffer addr MSB */
#define	T3_LOOP		(1<<5)	/* Bit 5: 	Set Loopback (Xmit) */
#define	T3_UNLOOP	(1<<4)	/* Bit 4: 	Unset Loopback (Xmit) */
#define	T3_MUX		(3<<2)	/* Bit 3..2:	Mux position */
#define	T3_VRAM		(3<<0)	/* Bit 1..0:	Virtual RAM buffer Address */

/* PCI card IDs */
/*
 * Note: The following 4 byte definitions shall not be used! Use OEM Concept!
 */
#define	PCI_VEND_ID0	0x48		/* PCI vendor ID (SysKonnect) */
#define	PCI_VEND_ID1	0x11		/* PCI vendor ID (SysKonnect) */
					/*		 (High byte) */
#define	PCI_DEV_ID0	0x00		/* PCI device ID */
#define	PCI_DEV_ID1	0x40		/* PCI device ID (High byte) */

/*#define PCI_CLASS	0x02*/		/* PCI class code: network device */
#define PCI_NW_CLASS	0x02		/* PCI class code: network device */
#define PCI_SUB_CLASS	0x02		/* PCI subclass ID: FDDI device */
#define PCI_PROG_INTFC	0x00		/* PCI programming Interface (=0) */

/*
 * address transmission from logical to physical offset address on board
 */
#define	FMA(a)	(0x0400|((a)<<2))	/* FORMAC+ (r/w) (SN3) */
#define	P1(a)	(0x0380|((a)<<2))	/* PLC1 (r/w) (DAS) */
#define	P2(a)	(0x0600|((a)<<2))	/* PLC2 (r/w) (covered by the SN3) */
#define PRA(a)	(B2_MAC_0 + (a))	/* configuration PROM (MAC address) */

/*
 * FlashProm specification
 */
#define	MAX_PAGES	0x20000L	/* Every byte has a single page */
#define	MAX_FADDR	1		/* 1 byte per page */

/*
 * Receive / Transmit Buffer Control word
 */
#define	BMU_OWN		(1UL<<31)	/* OWN bit: 0 == host, 1 == adapter */
#define	BMU_STF		(1L<<30)	/* Start of Frame ?		*/
#define	BMU_EOF		(1L<<29)	/* End of Frame ?		*/
#define	BMU_EN_IRQ_EOB	(1L<<28)	/* Enable "End of Buffer" IRQ	*/
#define	BMU_EN_IRQ_EOF	(1L<<27)	/* Enable "End of Frame" IRQ	*/
#define	BMU_DEV_0	(1L<<26)	/* RX: don't transfer to system mem */
#define BMU_SMT_TX	(1L<<25)	/* TX: if set, buffer type SMT_MBuf */
#define BMU_ST_BUF	(1L<<25)	/* RX: copy of start of frame */
#define BMU_UNUSED	(1L<<24)	/* Set if the Descr is curr unused */
#define BMU_SW		(3L<<24)	/* 2 Bits reserved for SW usage */
#define	BMU_CHECK	0x00550000L	/* To identify the control word */
#define	BMU_BBC		0x0000FFFFL	/* R/T Buffer Byte Count        */

/*
 * physical address offset + IO-Port base address
 */
#ifdef MEM_MAPPED_IO
#define	ADDR(a)		(char far *) smc->hw.iop+(a)
#define	ADDRS(smc,a)	(char far *) (smc)->hw.iop+(a)
#else
#define	ADDR(a)	(((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \
	(smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
	(smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
#define	ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \
	((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
	((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
#endif

/*
 * Define a macro to access the configuration space
 */
#define PCI_C(a)	ADDR(B3_CFG_SPC + (a))	/* PCI Config Space */

#define EXT_R(a)	ADDR(B6_EXT_REG + (a))	/* External Registers */

/*
 * Define some values needed for the MAC address (PROM)
 */
#define	SA_MAC		(0)	/* start addr. MAC_AD within the PROM */
#define	PRA_OFF		(0)	/* offset correction when 4th byte reading */

#define	SKFDDI_PSZ	8	/* address PROM size */

#define	FM_A(a)	ADDR(FMA(a))	/* FORMAC Plus physical addr */
#define	P1_A(a)	ADDR(P1(a))	/* PLC1 (r/w) */
#define	P2_A(a)	ADDR(P2(a))	/* PLC2 (r/w) (DAS) */
#define PR_A(a)	ADDR(PRA(a))	/* config. PROM (MAC address) */

/*
 * Macro to read the PROM
 */
#define	READ_PROM(a)	((u_char)inp(a))

#define	GET_PAGE(bank)	outpd(ADDR(B2_FAR),bank)
#define	VPP_ON()
#define	VPP_OFF()

/*
 * Note: Values of the Interrupt Source Register are defined above
 */
#define ISR_A		ADDR(B0_ISRC)
#define	GET_ISR()		inpd(ISR_A)
#define GET_ISR_SMP(iop)	inpd((iop)+B0_ISRC)
#define	CHECK_ISR()		(inpd(ISR_A) & inpd(ADDR(B0_IMSK)))
#define CHECK_ISR_SMP(iop)	(inpd((iop)+B0_ISRC) & inpd((iop)+B0_IMSK))

#define	BUS_CHECK()

/*
 * CLI_FBI:	Disable Board Interrupts
 * STI_FBI:	Enable Board Interrupts
 */
#ifndef UNIX
#define	CLI_FBI()	outpd(ADDR(B0_IMSK),0)
#else
#define	CLI_FBI(smc)	outpd(ADDRS((smc),B0_IMSK),0)
#endif

#ifndef UNIX
#define	STI_FBI()	outpd(ADDR(B0_IMSK),smc->hw.is_imask)
#else
#define	STI_FBI(smc)	outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
#endif

#define CLI_FBI_SMP(iop)	outpd((iop)+B0_IMSK,0)
#define	STI_FBI_SMP(smc,iop)	outpd((iop)+B0_IMSK,(smc)->hw.is_imask)

#endif	/* PCI */
/*--------------------------------------------------------------------------*/

/*
 * 12 bit transfer (dword) counter:
 *	(ISA:	2*trc = number of byte)
 *	(EISA:	4*trc = number of byte)
 *	(MCA:	4*trc = number of byte)
 */
#define	MAX_TRANS	(0x0fff)

/*
 * PC PIC
 */
#define	MST_8259 (0x20)
#define	SLV_8259 (0xA0)

#define TPS		(18)		/* ticks per second */

/*
 * error timer defs
 */
#define	TN		(4)	/* number of supported timer = TN+1 */
#define	SNPPND_TIME	(5)	/* buffer memory access over mem. data reg. */

#define	MAC_AD	0x405a0000

#define MODR1	FM_A(FM_MDREG1)	/* mode register 1 */
#define MODR2	FM_A(FM_MDREG2)	/* mode register 2 */

#define CMDR1	FM_A(FM_CMDREG1)	/* command register 1 */
#define CMDR2	FM_A(FM_CMDREG2)	/* command register 2 */


/*
 * function defines
 */
#define	CLEAR(io,mask)		outpw((io),inpw(io)&(~(mask)))
#define	SET(io,mask)		outpw((io),inpw(io)|(mask))
#define	GET(io,mask)		(inpw(io)&(mask))
#define	SETMASK(io,val,mask)	outpw((io),(inpw(io) & ~(mask)) | (val))

/*
 * PHY Port A (PA) = PLC 1
 * With SuperNet 3 PHY-A and PHY S are identical.
 */
#define	PLC(np,reg)	(((np) == PA) ? P2_A(reg) : P1_A(reg))

/*
 * set memory address register for write and read
 */
#define	MARW(ma)	outpw(FM_A(FM_MARW),(unsigned int)(ma))
#define	MARR(ma)	outpw(FM_A(FM_MARR),(unsigned int)(ma))

/*
 * read/write from/to memory data register
 */
/* write double word */
#define	MDRW(dd)	outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\
			outpw(FM_A(FM_MDRL),(unsigned int)(dd))

#ifndef WINNT
/* read double word */
#define	MDRR()		(((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL)))

/* read FORMAC+ 32-bit status register */
#define	GET_ST1()	(((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L)))
#define	GET_ST2()	(((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L)))
#ifdef	SUPERNET_3
#define	GET_ST3()	(((long)inpw(FM_A(FM_ST3U))<<16) + inpw(FM_A(FM_ST3L)))
#endif
#else
/* read double word */
#define MDRR()		inp2w((FM_A(FM_MDRU)),(FM_A(FM_MDRL)))

/* read FORMAC+ 32-bit status register */
#define GET_ST1()	inp2w((FM_A(FM_ST1U)),(FM_A(FM_ST1L)))
#define GET_ST2()	inp2w((FM_A(FM_ST2U)),(FM_A(FM_ST2L)))
#ifdef	SUPERNET_3
#define GET_ST3()	inp2w((FM_A(FM_ST3U)),(FM_A(FM_ST3L)))
#endif
#endif

/* Special timer macro for 82c54 */
				/* timer access over data bus bit 8..15 */
#define	OUT_82c54_TIMER(port,val)	outpw(TI_A(port),(val)<<8)
#define	IN_82c54_TIMER(port)		((inpw(TI_A(port))>>8) & 0xff)


#ifdef	DEBUG
#define	DB_MAC(mac,st) {if (debug_mac & 0x1)\
				printf("M") ;\
			if (debug_mac & 0x2)\
				printf("\tMAC %d status 0x%08lx\n",mac,st) ;\
			if (debug_mac & 0x4)\
				dp_mac(mac,st) ;\
}

#define	DB_PLC(p,iev) {	if (debug_plc & 0x1)\
				printf("P") ;\
			if (debug_plc & 0x2)\
				printf("\tPLC %s Int 0x%04x\n", \
					(p == PA) ? "A" : "B", iev) ;\
			if (debug_plc & 0x4)\
				dp_plc(p,iev) ;\
}

#define	DB_TIMER() {	if (debug_timer & 0x1)\
				printf("T") ;\
			if (debug_timer & 0x2)\
				printf("\tTimer ISR\n") ;\
}

#else	/* no DEBUG */

#define	DB_MAC(mac,st)
#define	DB_PLC(p,iev)
#define	DB_TIMER()

#endif	/* no DEBUG */

#define	INC_PTR(sp,cp,ep)	if (++cp == ep) cp = sp
/*
 * timer defs
 */
#define	COUNT(t)	((t)<<6)	/* counter */
#define	RW_OP(o)	((o)<<4)	/* read/write operation */
#define	TMODE(m)	((m)<<1)	/* timer mode */

#endif