skfbi.h

linux内核源码

#define	B0_MDREG3	0x0030	/* r/w Mode Register 3 */
#define	B0_ST3U		0x0034	/* read upper 16-bit of status reg 3 */
#define	B0_ST3L		0x0038	/* read lower 16-bit of status reg 3 */
#define	B0_IMSK3U	0x003c	/* r/w upper 16-bit of IMSK reg 3 */
#define	B0_IMSK3L	0x0040	/* r/w lower 16-bit of IMSK reg 3 */
#define	B0_IVR		0x0044	/* read Interrupt Vector register */
#define	B0_IMR		0x0048	/* r/w Interrupt mask register */
/* 0x4c	Hidden */

#define B0_CNTRL_A	0x0050	/* control register A (r/w) */
#define B0_CNTRL_B	0x0054	/* control register B (r/w) */
#define B0_INTR_MASK	0x0058	/* interrupt mask (r/w) */
#define B0_XMIT_VECTOR	0x005c	/* transmit vector register (r/w) */

#define B0_STATUS_A	0x0060	/* status register A (read only) */
#define B0_STATUS_B	0x0064	/* status register B (read only) */
#define B0_CNTRL_C	0x0068	/* control register C (r/w) */
#define	B0_MDREG1	0x006c	/* r/w Mode Register 1 */

#define	B0_R1_CSR	0x0070	/* 32 bit BMU control/status reg (rec q 1) */
#define	B0_R2_CSR	0x0074	/* 32 bit BMU control/status reg (rec q 2)(DV)*/
#define	B0_XA_CSR	0x0078	/* 32 bit BMU control/status reg (a xmit q) */
#define	B0_XS_CSR	0x007c	/* 32 bit BMU control/status reg (s xmit q) */

/*
 *	Bank 1
 *	- completely empty (this is the RAP Block window)
 *	Note: if RAP = 1 this page is reserved
 */

/*
 *	Bank 2
 */
#define	B2_MAC_0	0x0100	/*  8 bit MAC address Byte 0 */
#define	B2_MAC_1	0x0101	/*  8 bit MAC address Byte 1 */
#define	B2_MAC_2	0x0102	/*  8 bit MAC address Byte 2 */
#define	B2_MAC_3	0x0103	/*  8 bit MAC address Byte 3 */
#define	B2_MAC_4	0x0104	/*  8 bit MAC address Byte 4 */
#define	B2_MAC_5	0x0105	/*  8 bit MAC address Byte 5 */
#define	B2_MAC_6	0x0106	/*  8 bit MAC address Byte 6 (== 0) (DV) */
#define	B2_MAC_7	0x0107	/*  8 bit MAC address Byte 7 (== 0) (DV) */

#define B2_CONN_TYP	0x0108	/*  8 bit Connector type */
#define B2_PMD_TYP	0x0109	/*  8 bit PMD type */
				/* 0x010a - 0x010b:	reserved */
	/* Eprom registers are currently of no use */
#define B2_E_0		0x010c	/*  8 bit EPROM Byte 0 */
#define B2_E_1		0x010d	/*  8 bit EPROM Byte 1 */
#define B2_E_2		0x010e	/*  8 bit EPROM Byte 2 */
#define B2_E_3		0x010f	/*  8 bit EPROM Byte 3 */
#define B2_FAR		0x0110	/* 32 bit Flash-Prom Address Register/Counter */
#define B2_FDP		0x0114	/*  8 bit Flash-Prom Data Port */
				/* 0x0115 - 0x0117:	reserved */
#define B2_LD_CRTL	0x0118	/*  8 bit loader control */
#define B2_LD_TEST	0x0119	/*  8 bit loader test */
				/* 0x011a - 0x011f:	reserved */
#define B2_TI_INI	0x0120	/* 32 bit Timer init value */
#define B2_TI_VAL	0x0124	/* 32 bit Timer value */
#define B2_TI_CRTL	0x0128	/*  8 bit Timer control */
#define B2_TI_TEST	0x0129	/*  8 Bit Timer Test */
				/* 0x012a - 0x012f:	reserved */
#define B2_WDOG_INI	0x0130	/* 32 bit Watchdog init value */
#define B2_WDOG_VAL	0x0134	/* 32 bit Watchdog value */
#define B2_WDOG_CRTL	0x0138	/*  8 bit Watchdog control */
#define B2_WDOG_TEST	0x0139	/*  8 Bit Watchdog Test */
				/* 0x013a - 0x013f:	reserved */
#define B2_RTM_INI	0x0140	/* 32 bit RTM init value */
#define B2_RTM_VAL	0x0144	/* 32 bit RTM value */
#define B2_RTM_CRTL	0x0148	/*  8 bit RTM control */
#define B2_RTM_TEST	0x0149	/*  8 Bit RTM Test */

#define B2_TOK_COUNT	0x014c	/* (ML)	32 bit	Token Counter */
#define B2_DESC_ADDR_H	0x0150	/* (ML) 32 bit	Desciptor Base Addr Reg High */
#define B2_CTRL_2	0x0154	/* (ML)	 8 bit	Control Register 2 */
#define B2_IFACE_REG	0x0155	/* (ML)	 8 bit	Interface Register */
				/* 0x0156:		reserved */
#define B2_TST_CTRL_2	0x0157	/* (ML)  8 bit	Test Control Register 2 */
#define B2_I2C_CTRL	0x0158	/* (ML)	32 bit	I2C Control Register */
#define B2_I2C_DATA	0x015c	/* (ML) 32 bit	I2C Data Register */

#define B2_IRQ_MOD_INI	0x0160	/* (ML) 32 bit	IRQ Moderation Timer Init Reg. */
#define B2_IRQ_MOD_VAL	0x0164	/* (ML)	32 bit	IRQ Moderation Timer Value */
#define B2_IRQ_MOD_CTRL	0x0168	/* (ML)  8 bit	IRQ Moderation Timer Control */
#define B2_IRQ_MOD_TEST	0x0169	/* (ML)	 8 bit	IRQ Moderation Timer Test */
				/* 0x016a - 0x017f:	reserved */

/*
 *	Bank 3
 */
/*
 * This is a copy of the Configuration register file (lower half)
 */
#define B3_CFG_SPC	0x180

/*
 *	Bank 4
 */
#define B4_R1_D		0x0200	/* 	4*32 bit current receive Descriptor  */
#define B4_R1_DA	0x0210	/* 	32 bit current rec desc address	     */
#define B4_R1_AC	0x0214	/* 	32 bit current receive Address Count */
#define B4_R1_BC	0x0218	/*	32 bit current receive Byte Counter  */
#define B4_R1_CSR	0x021c	/* 	32 bit BMU Control/Status Register   */
#define B4_R1_F		0x0220	/* 	32 bit flag register		     */
#define B4_R1_T1	0x0224	/* 	32 bit Test Register 1		     */
#define B4_R1_T1_TR	0x0224	/* 	8 bit Test Register 1 TR	     */
#define B4_R1_T1_WR	0x0225	/* 	8 bit Test Register 1 WR	     */
#define B4_R1_T1_RD	0x0226	/* 	8 bit Test Register 1 RD	     */
#define B4_R1_T1_SV	0x0227	/* 	8 bit Test Register 1 SV	     */
#define B4_R1_T2	0x0228	/* 	32 bit Test Register 2		     */
#define B4_R1_T3	0x022c	/* 	32 bit Test Register 3		     */
#define B4_R1_DA_H	0x0230	/* (ML)	32 bit Curr Rx Desc Address High     */
#define B4_R1_AC_H	0x0234	/* (ML)	32 bit Curr Addr Counter High dword  */
				/* 0x0238 - 0x023f:	reserved	  */
				/* Receive queue 2 is removed on Monalisa */
#define B4_R2_D		0x0240	/* 4*32 bit current receive Descriptor	(q2) */
#define B4_R2_DA	0x0250	/* 32 bit current rec desc address	(q2) */
#define B4_R2_AC	0x0254	/* 32 bit current receive Address Count	(q2) */
#define B4_R2_BC	0x0258	/* 32 bit current receive Byte Counter	(q2) */
#define B4_R2_CSR	0x025c	/* 32 bit BMU Control/Status Register	(q2) */
#define B4_R2_F		0x0260	/* 32 bit flag register			(q2) */
#define B4_R2_T1	0x0264	/* 32 bit Test Register 1		(q2) */
#define B4_R2_T1_TR	0x0264	/* 8 bit Test Register 1 TR		(q2) */
#define B4_R2_T1_WR	0x0265	/* 8 bit Test Register 1 WR		(q2) */
#define B4_R2_T1_RD	0x0266	/* 8 bit Test Register 1 RD		(q2) */
#define B4_R2_T1_SV	0x0267	/* 8 bit Test Register 1 SV		(q2) */
#define B4_R2_T2	0x0268	/* 32 bit Test Register 2		(q2) */
#define B4_R2_T3	0x026c	/* 32 bit Test Register 3		(q2) */
				/* 0x0270 - 0x027c:	reserved */

/*
 *	Bank 5
 */
#define B5_XA_D		0x0280	/* 4*32 bit current transmit Descriptor	(xa) */
#define B5_XA_DA	0x0290	/* 32 bit current tx desc address	(xa) */
#define B5_XA_AC	0x0294	/* 32 bit current tx Address Count	(xa) */
#define B5_XA_BC	0x0298	/* 32 bit current tx Byte Counter	(xa) */
#define B5_XA_CSR	0x029c	/* 32 bit BMU Control/Status Register	(xa) */
#define B5_XA_F		0x02a0	/* 32 bit flag register			(xa) */
#define B5_XA_T1	0x02a4	/* 32 bit Test Register 1		(xa) */
#define B5_XA_T1_TR	0x02a4	/* 8 bit Test Register 1 TR		(xa) */
#define B5_XA_T1_WR	0x02a5	/* 8 bit Test Register 1 WR		(xa) */
#define B5_XA_T1_RD	0x02a6	/* 8 bit Test Register 1 RD		(xa) */
#define B5_XA_T1_SV	0x02a7	/* 8 bit Test Register 1 SV		(xa) */
#define B5_XA_T2	0x02a8	/* 32 bit Test Register 2		(xa) */
#define B5_XA_T3	0x02ac	/* 32 bit Test Register 3		(xa) */
#define B5_XA_DA_H	0x02b0	/* (ML)	32 bit Curr Tx Desc Address High     */
#define B5_XA_AC_H	0x02b4	/* (ML)	32 bit Curr Addr Counter High dword  */
				/* 0x02b8 - 0x02bc:	reserved */
#define B5_XS_D		0x02c0	/* 4*32 bit current transmit Descriptor	(xs) */
#define B5_XS_DA	0x02d0	/* 32 bit current tx desc address	(xs) */
#define B5_XS_AC	0x02d4	/* 32 bit current transmit Address Count(xs) */
#define B5_XS_BC	0x02d8	/* 32 bit current transmit Byte Counter	(xs) */
#define B5_XS_CSR	0x02dc	/* 32 bit BMU Control/Status Register	(xs) */
#define B5_XS_F		0x02e0	/* 32 bit flag register			(xs) */
#define B5_XS_T1	0x02e4	/* 32 bit Test Register 1		(xs) */
#define B5_XS_T1_TR	0x02e4	/* 8 bit Test Register 1 TR		(xs) */
#define B5_XS_T1_WR	0x02e5	/* 8 bit Test Register 1 WR		(xs) */
#define B5_XS_T1_RD	0x02e6	/* 8 bit Test Register 1 RD		(xs) */
#define B5_XS_T1_SV	0x02e7	/* 8 bit Test Register 1 SV		(xs) */
#define B5_XS_T2	0x02e8	/* 32 bit Test Register 2		(xs) */
#define B5_XS_T3	0x02ec	/* 32 bit Test Register 3		(xs) */
#define B5_XS_DA_H	0x02f0	/* (ML)	32 bit Curr Tx Desc Address High     */
#define B5_XS_AC_H	0x02f4	/* (ML)	32 bit Curr Addr Counter High dword  */
				/* 0x02f8 - 0x02fc:	reserved */

/*
 *	Bank 6
 */
/* External PLC-S registers (SN2 compatibility for DV) */
/* External registers (ML) */
#define B6_EXT_REG	0x300

/*
 *	Bank 7
 */
/* DAS PLC-S Registers */

/*
 *	Bank 8 - 15
 */
/* IFCP registers */

/*---------------------------------------------------------------------------*/
/* Definitions of the Bits in the registers */

/*	B0_RAP		16 bit register address port */
#define	RAP_RAP		0x0f	/* Bit 3..0:	0 = block0, .., f = block15 */

/*	B0_CTRL		8 bit control register */
#define CTRL_FDDI_CLR	(1<<7)	/* Bit 7: (ML)	Clear FDDI Reset */
#define CTRL_FDDI_SET	(1<<6)	/* Bit 6: (ML)	Set FDDI Reset */
#define	CTRL_HPI_CLR	(1<<5)	/* Bit 5:	Clear HPI SM reset */
#define	CTRL_HPI_SET	(1<<4)	/* Bit 4:	Set HPI SM reset */
#define	CTRL_MRST_CLR	(1<<3)	/* Bit 3:	Clear Master reset */
#define	CTRL_MRST_SET	(1<<2)	/* Bit 2:	Set Master reset */
#define	CTRL_RST_CLR	(1<<1)	/* Bit 1:	Clear Software reset */
#define	CTRL_RST_SET	(1<<0)	/* Bit 0:	Set Software reset */

/*	B0_DAS		8 Bit control register (DAS) */
#define BUS_CLOCK	(1<<7)	/* Bit 7: (ML)	Bus Clock 0/1 = 33/66MHz */
#define BUS_SLOT_SZ	(1<<6)	/* Bit 6: (ML)	Slot Size 0/1 = 32/64 bit slot*/
				/* Bit 5..4:	reserved */
#define	DAS_AVAIL	(1<<3)	/* Bit 3:	1 = DAS, 0 = SAS */
#define DAS_BYP_ST	(1<<2)	/* Bit 2:	1 = avail,SAS, 0 = not avail */
#define DAS_BYP_INS	(1<<1)	/* Bit 1:	1 = insert Bypass */
#define DAS_BYP_RMV	(1<<0)	/* Bit 0:	1 = remove Bypass */

/*	B0_LED		8 Bit LED register */
				/* Bit 7..6:	reserved */
#define LED_2_ON	(1<<5)	/* Bit 5:	1 = switch LED_2 on (left,gn)*/
#define LED_2_OFF	(1<<4)	/* Bit 4:	1 = switch LED_2 off */
#define LED_1_ON	(1<<3)	/* Bit 3:	1 = switch LED_1 on (mid,yel)*/
#define LED_1_OFF	(1<<2)	/* Bit 2:	1 = switch LED_1 off */
#define LED_0_ON	(1<<1)	/* Bit 1:	1 = switch LED_0 on (rght,gn)*/
#define LED_0_OFF	(1<<0)	/* Bit 0:	1 = switch LED_0 off */
/* This hardware defines are very ugly therefore we define some others */

#define LED_GA_ON	LED_2_ON	/* S port = A port */
#define LED_GA_OFF	LED_2_OFF	/* S port = A port */
#define LED_MY_ON	LED_1_ON
#define LED_MY_OFF	LED_1_OFF
#define LED_GB_ON	LED_0_ON
#define LED_GB_OFF	LED_0_OFF

/*	B0_TST_CTRL	8 bit test control register */
#define	TST_FRC_DPERR_MR	(1<<7)	/* Bit 7:  force DATAPERR on MST RE. */
#define	TST_FRC_DPERR_MW	(1<<6)	/* Bit 6:  force DATAPERR on MST WR. */
#define	TST_FRC_DPERR_TR	(1<<5)	/* Bit 5:  force DATAPERR on TRG RE. */
#define	TST_FRC_DPERR_TW	(1<<4)	/* Bit 4:  force DATAPERR on TRG WR. */
#define	TST_FRC_APERR_M		(1<<3)	/* Bit 3:  force ADDRPERR on MST     */
#define	TST_FRC_APERR_T		(1<<2)	/* Bit 2:  force ADDRPERR on TRG     */
#define	TST_CFG_WRITE_ON	(1<<1)	/* Bit 1:  ena configuration reg. WR */
#define	TST_CFG_WRITE_OFF	(1<<0)	/* Bit 0:  dis configuration reg. WR */

/*	B0_ISRC		32 bit Interrupt source register */
					/* Bit 31..28:	reserved	     */
#define IS_I2C_READY	(1L<<27)	/* Bit 27: (ML)	IRQ on end of I2C tx */
#define IS_IRQ_SW	(1L<<26)	/* Bit 26: (ML)	SW forced IRQ	     */
#define IS_EXT_REG	(1L<<25)	/* Bit 25: (ML) IRQ from external reg*/
#define	IS_IRQ_STAT	(1L<<24)	/* Bit 24:	IRQ status exception */
					/*   PERR, RMABORT, RTABORT DATAPERR */
#define	IS_IRQ_MST_ERR	(1L<<23)	/* Bit 23:	IRQ master error     */
					/*   RMABORT, RTABORT, DATAPERR	     */
#define	IS_TIMINT	(1L<<22)	/* Bit 22:	IRQ_TIMER	*/
#define	IS_TOKEN	(1L<<21)	/* Bit 21:	IRQ_RTM		*/
/*
 * Note: The DAS is our First Port (!=PA)
 */
#define	IS_PLINT1	(1L<<20)	/* Bit 20:	IRQ_PHY_DAS	*/
#define	IS_PLINT2	(1L<<19)	/* Bit 19:	IRQ_IFCP_4	*/
#define	IS_MINTR3	(1L<<18)	/* Bit 18:	IRQ_IFCP_3/IRQ_PHY */
#define	IS_MINTR2	(1L<<17)	/* Bit 17:	IRQ_IFCP_2/IRQ_MAC_2 */
#define	IS_MINTR1	(1L<<16)	/* Bit 16:	IRQ_IFCP_1/IRQ_MAC_1 */
/* Receive Queue 1 */
#define	IS_R1_P		(1L<<15)	/* Bit 15:	Parity Error (q1) */
#define	IS_R1_B		(1L<<14)	/* Bit 14:	End of Buffer (q1) */
#define	IS_R1_F		(1L<<13)	/* Bit 13:	End of Frame (q1) */
#define	IS_R1_C		(1L<<12)	/* Bit 12:	Encoding Error (q1) */
/* Receive Queue 2 */
#define	IS_R2_P		(1L<<11)	/* Bit 11: (DV)	Parity Error (q2) */
#define	IS_R2_B		(1L<<10)	/* Bit 10: (DV)	End of Buffer (q2) */
#define	IS_R2_F		(1L<<9)		/* Bit	9: (DV)	End of Frame (q2) */
#define	IS_R2_C		(1L<<8)		/* Bit	8: (DV)	Encoding Error (q2) */
/* Asynchronous Transmit queue */
					/* Bit  7:	reserved */
#define	IS_XA_B		(1L<<6)		/* Bit	6:	End of Buffer (xa) */
#define	IS_XA_F		(1L<<5)		/* Bit	5:	End of Frame (xa) */
#define	IS_XA_C		(1L<<4)		/* Bit	4:	Encoding Error (xa) */
/* Synchronous Transmit queue */
					/* Bit  3:	reserved */
#define	IS_XS_B		(1L<<2)		/* Bit	2:	End of Buffer (xs) */
#define	IS_XS_F		(1L<<1)		/* Bit	1:	End of Frame (xs) */
#define	IS_XS_C		(1L<<0)		/* Bit	0:	Encoding Error (xs) */

/*
 * Define all valid interrupt source Bits from GET_ISR ()
 */
#define	ALL_IRSR	0x01ffff77L	/* (DV) */
#define	ALL_IRSR_ML	0x0ffff077L	/* (ML) */


/*	B0_IMSK		32 bit Interrupt mask register */
/*
 * The Bit definnition of this register are the same as of the interrupt