b43legacy.h

linux内核源码

#ifndef B43legacy_H_
#define B43legacy_H_

#include <linux/hw_random.h>
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/stringify.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <asm/atomic.h>
#include <linux/io.h>

#include <linux/ssb/ssb.h>
#include <linux/ssb/ssb_driver_chipcommon.h>

#include <linux/wireless.h>
#include <net/mac80211.h>

#include "debugfs.h"
#include "leds.h"
#include "phy.h"


#define B43legacy_IRQWAIT_MAX_RETRIES	100

#define B43legacy_RX_MAX_SSI		60 /* best guess at max ssi */

/* MMIO offsets */
#define B43legacy_MMIO_DMA0_REASON	0x20
#define B43legacy_MMIO_DMA0_IRQ_MASK	0x24
#define B43legacy_MMIO_DMA1_REASON	0x28
#define B43legacy_MMIO_DMA1_IRQ_MASK	0x2C
#define B43legacy_MMIO_DMA2_REASON	0x30
#define B43legacy_MMIO_DMA2_IRQ_MASK	0x34
#define B43legacy_MMIO_DMA3_REASON	0x38
#define B43legacy_MMIO_DMA3_IRQ_MASK	0x3C
#define B43legacy_MMIO_DMA4_REASON	0x40
#define B43legacy_MMIO_DMA4_IRQ_MASK	0x44
#define B43legacy_MMIO_DMA5_REASON	0x48
#define B43legacy_MMIO_DMA5_IRQ_MASK	0x4C
#define B43legacy_MMIO_MACCTL		0x120
#define B43legacy_MMIO_STATUS_BITFIELD	0x120
#define B43legacy_MMIO_STATUS2_BITFIELD	0x124
#define B43legacy_MMIO_GEN_IRQ_REASON	0x128
#define B43legacy_MMIO_GEN_IRQ_MASK	0x12C
#define B43legacy_MMIO_RAM_CONTROL	0x130
#define B43legacy_MMIO_RAM_DATA		0x134
#define B43legacy_MMIO_PS_STATUS		0x140
#define B43legacy_MMIO_RADIO_HWENABLED_HI	0x158
#define B43legacy_MMIO_SHM_CONTROL	0x160
#define B43legacy_MMIO_SHM_DATA		0x164
#define B43legacy_MMIO_SHM_DATA_UNALIGNED	0x166
#define B43legacy_MMIO_XMITSTAT_0		0x170
#define B43legacy_MMIO_XMITSTAT_1		0x174
#define B43legacy_MMIO_REV3PLUS_TSF_LOW	0x180 /* core rev >= 3 only */
#define B43legacy_MMIO_REV3PLUS_TSF_HIGH	0x184 /* core rev >= 3 only */

/* 32-bit DMA */
#define B43legacy_MMIO_DMA32_BASE0	0x200
#define B43legacy_MMIO_DMA32_BASE1	0x220
#define B43legacy_MMIO_DMA32_BASE2	0x240
#define B43legacy_MMIO_DMA32_BASE3	0x260
#define B43legacy_MMIO_DMA32_BASE4	0x280
#define B43legacy_MMIO_DMA32_BASE5	0x2A0
/* 64-bit DMA */
#define B43legacy_MMIO_DMA64_BASE0	0x200
#define B43legacy_MMIO_DMA64_BASE1	0x240
#define B43legacy_MMIO_DMA64_BASE2	0x280
#define B43legacy_MMIO_DMA64_BASE3	0x2C0
#define B43legacy_MMIO_DMA64_BASE4	0x300
#define B43legacy_MMIO_DMA64_BASE5	0x340
/* PIO */
#define B43legacy_MMIO_PIO1_BASE		0x300
#define B43legacy_MMIO_PIO2_BASE		0x310
#define B43legacy_MMIO_PIO3_BASE		0x320
#define B43legacy_MMIO_PIO4_BASE		0x330

#define B43legacy_MMIO_PHY_VER		0x3E0
#define B43legacy_MMIO_PHY_RADIO		0x3E2
#define B43legacy_MMIO_PHY0		0x3E6
#define B43legacy_MMIO_ANTENNA		0x3E8
#define B43legacy_MMIO_CHANNEL		0x3F0
#define B43legacy_MMIO_CHANNEL_EXT	0x3F4
#define B43legacy_MMIO_RADIO_CONTROL	0x3F6
#define B43legacy_MMIO_RADIO_DATA_HIGH	0x3F8
#define B43legacy_MMIO_RADIO_DATA_LOW	0x3FA
#define B43legacy_MMIO_PHY_CONTROL	0x3FC
#define B43legacy_MMIO_PHY_DATA		0x3FE
#define B43legacy_MMIO_MACFILTER_CONTROL	0x420
#define B43legacy_MMIO_MACFILTER_DATA	0x422
#define B43legacy_MMIO_RCMTA_COUNT	0x43C /* Receive Match Transmitter Addr */
#define B43legacy_MMIO_RADIO_HWENABLED_LO	0x49A
#define B43legacy_MMIO_GPIO_CONTROL	0x49C
#define B43legacy_MMIO_GPIO_MASK		0x49E
#define B43legacy_MMIO_TSF_0		0x632 /* core rev < 3 only */
#define B43legacy_MMIO_TSF_1		0x634 /* core rev < 3 only */
#define B43legacy_MMIO_TSF_2		0x636 /* core rev < 3 only */
#define B43legacy_MMIO_TSF_3		0x638 /* core rev < 3 only */
#define B43legacy_MMIO_RNG		0x65A
#define B43legacy_MMIO_POWERUP_DELAY	0x6A8

/* SPROM boardflags_lo values */
#define B43legacy_BFL_PACTRL		0x0002
#define B43legacy_BFL_RSSI		0x0008
#define B43legacy_BFL_EXTLNA		0x1000

/* GPIO register offset, in both ChipCommon and PCI core. */
#define B43legacy_GPIO_CONTROL		0x6c

/* SHM Routing */
#define	B43legacy_SHM_SHARED		0x0001
#define	B43legacy_SHM_WIRELESS		0x0002
#define	B43legacy_SHM_HW		0x0004
#define	B43legacy_SHM_UCODE		0x0300

/* SHM Routing modifiers */
#define B43legacy_SHM_AUTOINC_R		0x0200 /* Read Auto-increment */
#define B43legacy_SHM_AUTOINC_W		0x0100 /* Write Auto-increment */
#define B43legacy_SHM_AUTOINC_RW	(B43legacy_SHM_AUTOINC_R | \
					 B43legacy_SHM_AUTOINC_W)

/* Misc SHM_SHARED offsets */
#define B43legacy_SHM_SH_WLCOREREV	0x0016 /* 802.11 core revision */
#define B43legacy_SHM_SH_HOSTFLO	0x005E /* Hostflags ucode opts (low) */
#define B43legacy_SHM_SH_HOSTFHI	0x0060 /* Hostflags ucode opts (high) */
/* SHM_SHARED crypto engine */
#define B43legacy_SHM_SH_KEYIDXBLOCK	0x05D4 /* Key index/algorithm block */
/* SHM_SHARED beacon variables */
#define B43legacy_SHM_SH_BEACPHYCTL	0x0054 /* Beacon PHY TX control word */
/* SHM_SHARED ACK/CTS control */
#define B43legacy_SHM_SH_ACKCTSPHYCTL	0x0022 /* ACK/CTS PHY control word */
/* SHM_SHARED probe response variables */
#define B43legacy_SHM_SH_PRPHYCTL	0x0188 /* Probe Resp PHY TX control */
#define B43legacy_SHM_SH_PRMAXTIME	0x0074 /* Probe Response max time */
/* SHM_SHARED rate tables */
/* SHM_SHARED microcode soft registers */
#define B43legacy_SHM_SH_UCODEREV	0x0000 /* Microcode revision */
#define B43legacy_SHM_SH_UCODEPATCH	0x0002 /* Microcode patchlevel */
#define B43legacy_SHM_SH_UCODEDATE	0x0004 /* Microcode date */
#define B43legacy_SHM_SH_UCODETIME	0x0006 /* Microcode time */

#define B43legacy_UCODEFLAGS_OFFSET     0x005E

/* Hardware Radio Enable masks */
#define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
#define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)

/* HostFlags. See b43legacy_hf_read/write() */
#define B43legacy_HF_SYMW		0x00000002 /* G-PHY SYM workaround */
#define B43legacy_HF_GDCW		0x00000020 /* G-PHY DV cancel filter */
#define B43legacy_HF_OFDMPABOOST	0x00000040 /* Enable PA boost OFDM */
#define B43legacy_HF_EDCF		0x00000100 /* on if WME/MAC suspended */

/* MacFilter offsets. */
#define B43legacy_MACFILTER_SELF	0x0000
#define B43legacy_MACFILTER_BSSID	0x0003
#define B43legacy_MACFILTER_MAC		0x0010

/* PHYVersioning */
#define B43legacy_PHYTYPE_B		0x01
#define B43legacy_PHYTYPE_G		0x02

/* PHYRegisters */
#define B43legacy_PHY_G_LO_CONTROL	0x0810
#define B43legacy_PHY_ILT_G_CTRL	0x0472
#define B43legacy_PHY_ILT_G_DATA1	0x0473
#define B43legacy_PHY_ILT_G_DATA2	0x0474
#define B43legacy_PHY_G_PCTL		0x0029
#define B43legacy_PHY_RADIO_BITFIELD	0x0401
#define B43legacy_PHY_G_CRS		0x0429
#define B43legacy_PHY_NRSSILT_CTRL	0x0803
#define B43legacy_PHY_NRSSILT_DATA	0x0804

/* RadioRegisters */
#define B43legacy_RADIOCTL_ID		0x01

/* MAC Control bitfield */
#define B43legacy_MACCTL_IHR_ENABLED	0x00000400 /* IHR Region Enabled */
#define B43legacy_MACCTL_INFRA		0x00020000 /* Infrastructure mode */
#define B43legacy_MACCTL_AP		0x00040000 /* AccessPoint mode */
#define B43legacy_MACCTL_BEACPROMISC	0x00100000 /* Beacon Promiscuous */
#define B43legacy_MACCTL_KEEP_BADPLCP	0x00200000 /* Keep bad PLCP frames */
#define B43legacy_MACCTL_KEEP_CTL	0x00400000 /* Keep control frames */
#define B43legacy_MACCTL_KEEP_BAD	0x00800000 /* Keep bad frames (FCS) */
#define B43legacy_MACCTL_PROMISC	0x01000000 /* Promiscuous mode */
#define B43legacy_MACCTL_GMODE		0x80000000 /* G Mode */

/* StatusBitField */
#define B43legacy_SBF_MAC_ENABLED	0x00000001
#define B43legacy_SBF_CORE_READY	0x00000004
#define B43legacy_SBF_400		0x00000400 /*FIXME: fix name*/
#define B43legacy_SBF_XFER_REG_BYTESWAP	0x00010000
#define B43legacy_SBF_MODE_NOTADHOC	0x00020000
#define B43legacy_SBF_MODE_AP		0x00040000
#define B43legacy_SBF_RADIOREG_LOCK	0x00080000
#define B43legacy_SBF_MODE_MONITOR	0x00400000
#define B43legacy_SBF_MODE_PROMISC	0x01000000
#define B43legacy_SBF_PS1		0x02000000
#define B43legacy_SBF_PS2		0x04000000
#define B43legacy_SBF_NO_SSID_BCAST	0x08000000
#define B43legacy_SBF_TIME_UPDATE	0x10000000

/* 802.11 core specific TM State Low flags */
#define B43legacy_TMSLOW_GMODE		0x20000000 /* G Mode Enable */
#define B43legacy_TMSLOW_PLLREFSEL	0x00200000 /* PLL Freq Ref Select */
#define B43legacy_TMSLOW_MACPHYCLKEN	0x00100000 /* MAC PHY Clock Ctrl Enbl */
#define B43legacy_TMSLOW_PHYRESET	0x00080000 /* PHY Reset */
#define B43legacy_TMSLOW_PHYCLKEN	0x00040000 /* PHY Clock Enable */

/* 802.11 core specific TM State High flags */
#define B43legacy_TMSHIGH_FCLOCK	0x00040000 /* Fast Clock Available */
#define B43legacy_TMSHIGH_GPHY		0x00010000 /* G-PHY avail (rev >= 5) */

#define B43legacy_UCODEFLAG_AUTODIV       0x0001

/* Generic-Interrupt reasons. */
#define B43legacy_IRQ_MAC_SUSPENDED	0x00000001
#define B43legacy_IRQ_BEACON		0x00000002
#define B43legacy_IRQ_TBTT_INDI		0x00000004 /* Target Beacon Transmit Time */
#define B43legacy_IRQ_BEACON_TX_OK	0x00000008
#define B43legacy_IRQ_BEACON_CANCEL	0x00000010
#define B43legacy_IRQ_ATIM_END		0x00000020
#define B43legacy_IRQ_PMQ		0x00000040
#define B43legacy_IRQ_PIO_WORKAROUND	0x00000100
#define B43legacy_IRQ_MAC_TXERR		0x00000200
#define B43legacy_IRQ_PHY_TXERR		0x00000800
#define B43legacy_IRQ_PMEVENT		0x00001000
#define B43legacy_IRQ_TIMER0		0x00002000
#define B43legacy_IRQ_TIMER1		0x00004000
#define B43legacy_IRQ_DMA		0x00008000
#define B43legacy_IRQ_TXFIFO_FLUSH_OK	0x00010000
#define B43legacy_IRQ_CCA_MEASURE_OK	0x00020000
#define B43legacy_IRQ_NOISESAMPLE_OK	0x00040000
#define B43legacy_IRQ_UCODE_DEBUG	0x08000000
#define B43legacy_IRQ_RFKILL		0x10000000
#define B43legacy_IRQ_TX_OK		0x20000000
#define B43legacy_IRQ_PHY_G_CHANGED	0x40000000
#define B43legacy_IRQ_TIMEOUT		0x80000000

#define B43legacy_IRQ_ALL		0xFFFFFFFF
#define B43legacy_IRQ_MASKTEMPLATE	(B43legacy_IRQ_MAC_SUSPENDED |	\
					 B43legacy_IRQ_BEACON |		\
					 B43legacy_IRQ_TBTT_INDI |	\
					 B43legacy_IRQ_ATIM_END |	\
					 B43legacy_IRQ_PMQ |		\
					 B43legacy_IRQ_MAC_TXERR |	\
					 B43legacy_IRQ_PHY_TXERR |	\
					 B43legacy_IRQ_DMA |		\
					 B43legacy_IRQ_TXFIFO_FLUSH_OK | \
					 B43legacy_IRQ_NOISESAMPLE_OK | \
					 B43legacy_IRQ_UCODE_DEBUG |	\
					 B43legacy_IRQ_RFKILL |		\
					 B43legacy_IRQ_TX_OK)

/* Device specific rate values.
 * The actual values defined here are (rate_in_mbps * 2).
 * Some code depends on this. Don't change it. */
#define B43legacy_CCK_RATE_1MB		2
#define B43legacy_CCK_RATE_2MB		4
#define B43legacy_CCK_RATE_5MB		11
#define B43legacy_CCK_RATE_11MB		22
#define B43legacy_OFDM_RATE_6MB		12
#define B43legacy_OFDM_RATE_9MB		18
#define B43legacy_OFDM_RATE_12MB	24
#define B43legacy_OFDM_RATE_18MB	36
#define B43legacy_OFDM_RATE_24MB	48
#define B43legacy_OFDM_RATE_36MB	72
#define B43legacy_OFDM_RATE_48MB	96
#define B43legacy_OFDM_RATE_54MB	108
/* Convert a b43legacy rate value to a rate in 100kbps */
#define B43legacy_RATE_TO_100KBPS(rate)	(((rate) * 10) / 2)


#define B43legacy_DEFAULT_SHORT_RETRY_LIMIT	7
#define B43legacy_DEFAULT_LONG_RETRY_LIMIT	4

/* Max size of a security key */
#define B43legacy_SEC_KEYSIZE		16
/* Security algorithms. */
enum {
	B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
	B43legacy_SEC_ALGO_WEP40,
	B43legacy_SEC_ALGO_TKIP,
	B43legacy_SEC_ALGO_AES,
	B43legacy_SEC_ALGO_WEP104,
	B43legacy_SEC_ALGO_AES_LEGACY,
};

/* Core Information Registers */
#define B43legacy_CIR_BASE                0xf00
#define B43legacy_CIR_SBTPSFLAG           (B43legacy_CIR_BASE + 0x18)
#define B43legacy_CIR_SBIMSTATE           (B43legacy_CIR_BASE + 0x90)
#define B43legacy_CIR_SBINTVEC            (B43legacy_CIR_BASE + 0x94)
#define B43legacy_CIR_SBTMSTATELOW        (B43legacy_CIR_BASE + 0x98)
#define B43legacy_CIR_SBTMSTATEHIGH       (B43legacy_CIR_BASE + 0x9c)
#define B43legacy_CIR_SBIMCONFIGLOW       (B43legacy_CIR_BASE + 0xa8)
#define B43legacy_CIR_SB_ID_HI            (B43legacy_CIR_BASE + 0xfc)

/* sbtmstatehigh state flags */
#define B43legacy_SBTMSTATEHIGH_SERROR		0x00000001
#define B43legacy_SBTMSTATEHIGH_BUSY		0x00000004
#define B43legacy_SBTMSTATEHIGH_TIMEOUT		0x00000020
#define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL	0x00010000
#define B43legacy_SBTMSTATEHIGH_COREFLAGS	0x1FFF0000
#define B43legacy_SBTMSTATEHIGH_DMA64BIT	0x10000000
#define B43legacy_SBTMSTATEHIGH_GATEDCLK	0x20000000
#define B43legacy_SBTMSTATEHIGH_BISTFAILED	0x40000000
#define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE	0x80000000

/* sbimstate flags */
#define B43legacy_SBIMSTATE_IB_ERROR		0x20000
#define B43legacy_SBIMSTATE_TIMEOUT		0x40000

#define PFX		KBUILD_MODNAME ": "
#ifdef assert
# undef assert
#endif
#ifdef CONFIG_B43LEGACY_DEBUG
# define B43legacy_WARN_ON(expr)					\
	do {								\
		if (unlikely((expr))) {					\
			printk(KERN_INFO PFX "Test (%s) failed at:"	\
					      " %s:%d:%s()\n",		\
					      #expr, __FILE__,		\
					      __LINE__, __FUNCTION__);	\
		}							\
	} while (0)
# define B43legacy_BUG_ON(expr)						\
	do {								\
		if (unlikely((expr))) {					\
			printk(KERN_INFO PFX "Test (%s) failed\n",	\
					      #expr);			\
			BUG_ON(expr);					\
		}							\
	} while (0)
# define B43legacy_DEBUG	1
#else
# define B43legacy_WARN_ON(x)	do { /* nothing */ } while (0)
# define B43legacy_BUG_ON(x)	do { /* nothing */ } while (0)
# define B43legacy_DEBUG	0
#endif


struct net_device;
struct pci_dev;
struct b43legacy_dmaring;
struct b43legacy_pioqueue;

/* The firmware file header */
#define B43legacy_FW_TYPE_UCODE	'u'
#define B43legacy_FW_TYPE_PCM	'p'
#define B43legacy_FW_TYPE_IV	'i'
struct b43legacy_fw_header {
	/* File type */
	u8 type;
	/* File format version */
	u8 ver;
	u8 __padding[2];
	/* Size of the data. For ucode and PCM this is in bytes.
	 * For IV this is number-of-ivs. */
	__be32 size;
} __attribute__((__packed__));

/* Initial Value file format */
#define B43legacy_IV_OFFSET_MASK	0x7FFF
#define B43legacy_IV_32BIT		0x8000
struct b43legacy_iv {
	__be16 offset_size;
	union {
		__be16 d16;
		__be32 d32;
	} data __attribute__((__packed__));
} __attribute__((__packed__));

#define B43legacy_PHYMODE(phytype)	(1 << (phytype))
#define B43legacy_PHYMODE_B		B43legacy_PHYMODE	\
					((B43legacy_PHYTYPE_B))
#define B43legacy_PHYMODE_G		B43legacy_PHYMODE	\
					((B43legacy_PHYTYPE_G))

/* Value pair to measure the LocalOscillator. */
struct b43legacy_lopair {
	s8 low;
	s8 high;
	u8 used:1;
};
#define B43legacy_LO_COUNT	(14*4)

struct b43legacy_phy {
	/* Possible PHYMODEs on this PHY */
	u8 possible_phymodes;
	/* GMODE bit enabled in MACCTL? */
	bool gmode;
	/* Possible ieee80211 subsystem hwmodes for this PHY.
	 * Which mode is selected, depends on thr GMODE enabled bit */
#define B43legacy_MAX_PHYHWMODES	2
	struct ieee80211_hw_mode hwmodes[B43legacy_MAX_PHYHWMODES];

	/* Analog Type */
	u8 analog;
	/* B43legacy_PHYTYPE_ */
	u8 type;
	/* PHY revision number. */
	u8 rev;

	u16 antenna_diversity;
	u16 savedpctlreg;
	/* Radio versioning */
	u16 radio_manuf;	/* Radio manufacturer */
	u16 radio_ver;		/* Radio version */
	u8 calibrated:1;
	u8 radio_rev;		/* Radio revision */

	bool locked;		/* Only used in b43legacy_phy_{un}lock() */
	bool dyn_tssi_tbl;	/* tssi2dbm is kmalloc()ed. */