📄 iwl-4965-hw.h
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#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)/* RSSR Area - Rx shared ctrl & status registers */#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008)/* TCSR */#define IWL_FH_TCSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xD00)#define IWL_FH_TCSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xE60)#define IWL_FH_TCSR_CHNL_NUM (7)#define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl)/* TSSR Area - Tx shared status registers *//* TSSR */#define IWL_FH_TSSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEA0)#define IWL_FH_TSSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEC0)#define IWL_FH_TSSR_TX_MSG_CONFIG_REG (IWL_FH_TSSR_LOWER_BOUND + 0x008)#define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010)#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_64B (0x00000000)#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_256B (0x00000800)#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_512B (0x00000C00)#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)#define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \ ((1 << (_chnl)) << 24)#define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \ ((1 << (_chnl)) << 16)#define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \ (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \ IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))/* TCSR: tx_config register values */#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_ARC (0x00000002)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)/* RCSR: channel 0 rx_config register defines */#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)#define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT (16)/* RCSR: rx_config register values */#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)#define IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)/* RCSR channel 0 config register values */#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)/* RSCSR: defs used in normal mode */#define FH_RSCSR_CHNL0_RBDCB_WPTR_MASK (0x00000FFF) /* bits 0-11 */#define SCD_WIN_SIZE 64#define SCD_FRAME_LIMIT 64/* memory mapped registers */#define SCD_START_OFFSET 0xa02c00#define SCD_SRAM_BASE_ADDR (SCD_START_OFFSET + 0x0)#define SCD_EMPTY_BITS (SCD_START_OFFSET + 0x4)#define SCD_DRAM_BASE_ADDR (SCD_START_OFFSET + 0x10)#define SCD_AIT (SCD_START_OFFSET + 0x18)#define SCD_TXFACT (SCD_START_OFFSET + 0x1c)#define SCD_QUEUE_WRPTR(x) (SCD_START_OFFSET + 0x24 + (x) * 4)#define SCD_QUEUE_RDPTR(x) (SCD_START_OFFSET + 0x64 + (x) * 4)#define SCD_SETQUEUENUM (SCD_START_OFFSET + 0xa4)#define SCD_SET_TXSTAT_TXED (SCD_START_OFFSET + 0xa8)#define SCD_SET_TXSTAT_DONE (SCD_START_OFFSET + 0xac)#define SCD_SET_TXSTAT_NOT_SCHD (SCD_START_OFFSET + 0xb0)#define SCD_DECREASE_CREDIT (SCD_START_OFFSET + 0xb4)#define SCD_DECREASE_SCREDIT (SCD_START_OFFSET + 0xb8)#define SCD_LOAD_CREDIT (SCD_START_OFFSET + 0xbc)#define SCD_LOAD_SCREDIT (SCD_START_OFFSET + 0xc0)#define SCD_BAR (SCD_START_OFFSET + 0xc4)#define SCD_BAR_DW0 (SCD_START_OFFSET + 0xc8)#define SCD_BAR_DW1 (SCD_START_OFFSET + 0xcc)#define SCD_QUEUECHAIN_SEL (SCD_START_OFFSET + 0xd0)#define SCD_QUERY_REQ (SCD_START_OFFSET + 0xd8)#define SCD_QUERY_RES (SCD_START_OFFSET + 0xdc)#define SCD_PENDING_FRAMES (SCD_START_OFFSET + 0xe0)#define SCD_INTERRUPT_MASK (SCD_START_OFFSET + 0xe4)#define SCD_INTERRUPT_THRESHOLD (SCD_START_OFFSET + 0xe8)#define SCD_QUERY_MIN_FRAME_SIZE (SCD_START_OFFSET + 0x100)#define SCD_QUEUE_STATUS_BITS(x) (SCD_START_OFFSET + 0x104 + (x) * 4)/* SRAM structures */#define SCD_CONTEXT_DATA_OFFSET 0x380#define SCD_TX_STTS_BITMAP_OFFSET 0x400#define SCD_TRANSLATE_TBL_OFFSET 0x500#define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8))#define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)#define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \ ((1<<(hi))|((1<<(hi))-(1<<(lo))))#define SCD_MODE_REG_BIT_SEARCH_MODE (1<<0)#define SCD_MODE_REG_BIT_SBYP_MODE (1<<1)#define SCD_TXFIFO_POS_TID (0)#define SCD_TXFIFO_POS_RA (4)#define SCD_QUEUE_STTS_REG_POS_ACTIVE (0)#define SCD_QUEUE_STTS_REG_POS_TXF (1)#define SCD_QUEUE_STTS_REG_POS_WSL (5)#define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)#define SCD_QUEUE_STTS_REG_MSK (0x0007FC00)#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)#define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)#define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)#define SCD_QUEUE_CTX_REG1_CREDIT_POS (8)#define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)#define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010)#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)static inline u8 iwl_hw_get_rate(__le32 rate_n_flags){ return le32_to_cpu(rate_n_flags) & 0xFF;}static inline u16 iwl_hw_get_rate_n_flags(__le32 rate_n_flags){ return le32_to_cpu(rate_n_flags) & 0xFFFF;}static inline __le32 iwl_hw_set_rate_n_flags(u8 rate, u16 flags){ return cpu_to_le32(flags|(u16)rate);}struct iwl_tfd_frame_data { __le32 tb1_addr; __le32 val1; /* __le32 ptb1_32_35:4; */#define IWL_tb1_addr_hi_POS 0#define IWL_tb1_addr_hi_LEN 4#define IWL_tb1_addr_hi_SYM val1 /* __le32 tb_len1:12; */#define IWL_tb1_len_POS 4#define IWL_tb1_len_LEN 12#define IWL_tb1_len_SYM val1 /* __le32 ptb2_0_15:16; */#define IWL_tb2_addr_lo16_POS 16#define IWL_tb2_addr_lo16_LEN 16#define IWL_tb2_addr_lo16_SYM val1 __le32 val2; /* __le32 ptb2_16_35:20; */#define IWL_tb2_addr_hi20_POS 0#define IWL_tb2_addr_hi20_LEN 20#define IWL_tb2_addr_hi20_SYM val2 /* __le32 tb_len2:12; */#define IWL_tb2_len_POS 20#define IWL_tb2_len_LEN 12#define IWL_tb2_len_SYM val2} __attribute__ ((packed));struct iwl_tfd_frame { __le32 val0; /* __le32 rsvd1:24; */ /* __le32 num_tbs:5; */#define IWL_num_tbs_POS 24#define IWL_num_tbs_LEN 5#define IWL_num_tbs_SYM val0 /* __le32 rsvd2:1; */ /* __le32 padding:2; */ struct iwl_tfd_frame_data pa[10]; __le32 reserved;} __attribute__ ((packed));#define IWL4965_MAX_WIN_SIZE 64#define IWL4965_QUEUE_SIZE 256#define IWL4965_NUM_FIFOS 7#define IWL_MAX_NUM_QUEUES 16struct iwl4965_queue_byte_cnt_entry { __le16 val; /* __le16 byte_cnt:12; */#define IWL_byte_cnt_POS 0#define IWL_byte_cnt_LEN 12#define IWL_byte_cnt_SYM val /* __le16 rsvd:4; */} __attribute__ ((packed));struct iwl4965_sched_queue_byte_cnt_tbl { struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE + IWL4965_MAX_WIN_SIZE]; u8 dont_care[1024 - (IWL4965_QUEUE_SIZE + IWL4965_MAX_WIN_SIZE) * sizeof(__le16)];} __attribute__ ((packed));/* Base physical address of iwl_shared is provided to SCD_DRAM_BASE_ADDR * and &iwl_shared.val0 is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG */struct iwl_shared { struct iwl4965_sched_queue_byte_cnt_tbl queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES]; __le32 val0; /* __le32 rb_closed_stts_rb_num:12; */#define IWL_rb_closed_stts_rb_num_POS 0#define IWL_rb_closed_stts_rb_num_LEN 12#define IWL_rb_closed_stts_rb_num_SYM val0 /* __le32 rsrv1:4; */ /* __le32 rb_closed_stts_rx_frame_num:12; */#define IWL_rb_closed_stts_rx_frame_num_POS 16#define IWL_rb_closed_stts_rx_frame_num_LEN 12#define IWL_rb_closed_stts_rx_frame_num_SYM val0 /* __le32 rsrv2:4; */ __le32 val1; /* __le32 frame_finished_stts_rb_num:12; */#define IWL_frame_finished_stts_rb_num_POS 0#define IWL_frame_finished_stts_rb_num_LEN 12#define IWL_frame_finished_stts_rb_num_SYM val1 /* __le32 rsrv3:4; */ /* __le32 frame_finished_stts_rx_frame_num:12; */#define IWL_frame_finished_stts_rx_frame_num_POS 16#define IWL_frame_finished_stts_rx_frame_num_LEN 12#define IWL_frame_finished_stts_rx_frame_num_SYM val1 /* __le32 rsrv4:4; */ __le32 padding1; /* so that allocation will be aligned to 16B */ __le32 padding2;} __attribute__ ((packed));#endif /* __iwl_4965_hw_h__ */⌨️ 快捷键说明
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