📄 rt61pci.h

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 * TSF_TICKING: Enable TSF auto counting. * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. * BEACON_GEN: Enable beacon generator. */#define TXRX_CSR9			0x3064#define TXRX_CSR9_BEACON_INTERVAL	FIELD32(0x0000ffff)#define TXRX_CSR9_TSF_TICKING		FIELD32(0x00010000)#define TXRX_CSR9_TSF_SYNC		FIELD32(0x00060000)#define TXRX_CSR9_TBTT_ENABLE		FIELD32(0x00080000)#define TXRX_CSR9_BEACON_GEN		FIELD32(0x00100000)#define TXRX_CSR9_TIMESTAMP_COMPENSATE	FIELD32(0xff000000)/* * TXRX_CSR10: BEACON alignment. */#define TXRX_CSR10			0x3068/* * TXRX_CSR11: AES mask. */#define TXRX_CSR11			0x306c/* * TXRX_CSR12: TSF low 32. */#define TXRX_CSR12			0x3070#define TXRX_CSR12_LOW_TSFTIMER		FIELD32(0xffffffff)/* * TXRX_CSR13: TSF high 32. */#define TXRX_CSR13			0x3074#define TXRX_CSR13_HIGH_TSFTIMER	FIELD32(0xffffffff)/* * TXRX_CSR14: TBTT timer. */#define TXRX_CSR14			0x3078/* * TXRX_CSR15: TKIP MIC priority byte "AND" mask. */#define TXRX_CSR15			0x307c/* * PHY control registers. * Some values are set in TU, whereas 1 TU == 1024 us. *//* * PHY_CSR0: RF/PS control. */#define PHY_CSR0			0x3080#define PHY_CSR0_PA_PE_BG		FIELD32(0x00010000)#define PHY_CSR0_PA_PE_A		FIELD32(0x00020000)/* * PHY_CSR1 */#define PHY_CSR1			0x3084/* * PHY_CSR2: Pre-TX BBP control. */#define PHY_CSR2			0x3088/* * PHY_CSR3: BBP serial control register. * VALUE: Register value to program into BBP. * REG_NUM: Selected BBP register. * READ_CONTROL: 0: Write BBP, 1: Read BBP. * BUSY: 1: ASIC is busy execute BBP programming. */#define PHY_CSR3			0x308c#define PHY_CSR3_VALUE			FIELD32(0x000000ff)#define PHY_CSR3_REGNUM			FIELD32(0x00007f00)#define PHY_CSR3_READ_CONTROL		FIELD32(0x00008000)#define PHY_CSR3_BUSY			FIELD32(0x00010000)/* * PHY_CSR4: RF serial control register * VALUE: Register value (include register id) serial out to RF/IF chip. * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22). * IF_SELECT: 1: select IF to program, 0: select RF to program. * PLL_LD: RF PLL_LD status. * BUSY: 1: ASIC is busy execute RF programming. */#define PHY_CSR4			0x3090#define PHY_CSR4_VALUE			FIELD32(0x00ffffff)#define PHY_CSR4_NUMBER_OF_BITS		FIELD32(0x1f000000)#define PHY_CSR4_IF_SELECT		FIELD32(0x20000000)#define PHY_CSR4_PLL_LD			FIELD32(0x40000000)#define PHY_CSR4_BUSY			FIELD32(0x80000000)/* * PHY_CSR5: RX to TX signal switch timing control. */#define PHY_CSR5			0x3094#define PHY_CSR5_IQ_FLIP		FIELD32(0x00000004)/* * PHY_CSR6: TX to RX signal timing control. */#define PHY_CSR6			0x3098#define PHY_CSR6_IQ_FLIP		FIELD32(0x00000004)/* * PHY_CSR7: TX DAC switching timing control. */#define PHY_CSR7			0x309c/* * Security control register. *//* * SEC_CSR0: Shared key table control. */#define SEC_CSR0			0x30a0#define SEC_CSR0_BSS0_KEY0_VALID	FIELD32(0x00000001)#define SEC_CSR0_BSS0_KEY1_VALID	FIELD32(0x00000002)#define SEC_CSR0_BSS0_KEY2_VALID	FIELD32(0x00000004)#define SEC_CSR0_BSS0_KEY3_VALID	FIELD32(0x00000008)#define SEC_CSR0_BSS1_KEY0_VALID	FIELD32(0x00000010)#define SEC_CSR0_BSS1_KEY1_VALID	FIELD32(0x00000020)#define SEC_CSR0_BSS1_KEY2_VALID	FIELD32(0x00000040)#define SEC_CSR0_BSS1_KEY3_VALID	FIELD32(0x00000080)#define SEC_CSR0_BSS2_KEY0_VALID	FIELD32(0x00000100)#define SEC_CSR0_BSS2_KEY1_VALID	FIELD32(0x00000200)#define SEC_CSR0_BSS2_KEY2_VALID	FIELD32(0x00000400)#define SEC_CSR0_BSS2_KEY3_VALID	FIELD32(0x00000800)#define SEC_CSR0_BSS3_KEY0_VALID	FIELD32(0x00001000)#define SEC_CSR0_BSS3_KEY1_VALID	FIELD32(0x00002000)#define SEC_CSR0_BSS3_KEY2_VALID	FIELD32(0x00004000)#define SEC_CSR0_BSS3_KEY3_VALID	FIELD32(0x00008000)/* * SEC_CSR1: Shared key table security mode register. */#define SEC_CSR1			0x30a4#define SEC_CSR1_BSS0_KEY0_CIPHER_ALG	FIELD32(0x00000007)#define SEC_CSR1_BSS0_KEY1_CIPHER_ALG	FIELD32(0x00000070)#define SEC_CSR1_BSS0_KEY2_CIPHER_ALG	FIELD32(0x00000700)#define SEC_CSR1_BSS0_KEY3_CIPHER_ALG	FIELD32(0x00007000)#define SEC_CSR1_BSS1_KEY0_CIPHER_ALG	FIELD32(0x00070000)#define SEC_CSR1_BSS1_KEY1_CIPHER_ALG	FIELD32(0x00700000)#define SEC_CSR1_BSS1_KEY2_CIPHER_ALG	FIELD32(0x07000000)#define SEC_CSR1_BSS1_KEY3_CIPHER_ALG	FIELD32(0x70000000)/* * Pairwise key table valid bitmap registers. * SEC_CSR2: pairwise key table valid bitmap 0. * SEC_CSR3: pairwise key table valid bitmap 1. */#define SEC_CSR2			0x30a8#define SEC_CSR3			0x30ac/* * SEC_CSR4: Pairwise key table lookup control. */#define SEC_CSR4			0x30b0/* * SEC_CSR5: shared key table security mode register. */#define SEC_CSR5			0x30b4#define SEC_CSR5_BSS2_KEY0_CIPHER_ALG	FIELD32(0x00000007)#define SEC_CSR5_BSS2_KEY1_CIPHER_ALG	FIELD32(0x00000070)#define SEC_CSR5_BSS2_KEY2_CIPHER_ALG	FIELD32(0x00000700)#define SEC_CSR5_BSS2_KEY3_CIPHER_ALG	FIELD32(0x00007000)#define SEC_CSR5_BSS3_KEY0_CIPHER_ALG	FIELD32(0x00070000)#define SEC_CSR5_BSS3_KEY1_CIPHER_ALG	FIELD32(0x00700000)#define SEC_CSR5_BSS3_KEY2_CIPHER_ALG	FIELD32(0x07000000)#define SEC_CSR5_BSS3_KEY3_CIPHER_ALG	FIELD32(0x70000000)/* * STA control registers. *//* * STA_CSR0: RX PLCP error count & RX FCS error count. */#define STA_CSR0			0x30c0#define STA_CSR0_FCS_ERROR		FIELD32(0x0000ffff)#define STA_CSR0_PLCP_ERROR		FIELD32(0xffff0000)/* * STA_CSR1: RX False CCA count & RX LONG frame count. */#define STA_CSR1			0x30c4#define STA_CSR1_PHYSICAL_ERROR		FIELD32(0x0000ffff)#define STA_CSR1_FALSE_CCA_ERROR	FIELD32(0xffff0000)/* * STA_CSR2: TX Beacon count and RX FIFO overflow count. */#define STA_CSR2			0x30c8#define STA_CSR2_RX_FIFO_OVERFLOW_COUNT	FIELD32(0x0000ffff)#define STA_CSR2_RX_OVERFLOW_COUNT	FIELD32(0xffff0000)/* * STA_CSR3: TX Beacon count. */#define STA_CSR3			0x30cc#define STA_CSR3_TX_BEACON_COUNT	FIELD32(0x0000ffff)/* * STA_CSR4: TX Result status register. * VALID: 1:This register contains a valid TX result. */#define STA_CSR4			0x30d0#define STA_CSR4_VALID			FIELD32(0x00000001)#define STA_CSR4_TX_RESULT		FIELD32(0x0000000e)#define STA_CSR4_RETRY_COUNT		FIELD32(0x000000f0)#define STA_CSR4_PID_SUBTYPE		FIELD32(0x00001f00)#define STA_CSR4_PID_TYPE		FIELD32(0x0000e000)#define STA_CSR4_TXRATE			FIELD32(0x000f0000)/* * QOS control registers. *//* * QOS_CSR0: TXOP holder MAC address register. */#define QOS_CSR0			0x30e0#define QOS_CSR0_BYTE0			FIELD32(0x000000ff)#define QOS_CSR0_BYTE1			FIELD32(0x0000ff00)#define QOS_CSR0_BYTE2			FIELD32(0x00ff0000)#define QOS_CSR0_BYTE3			FIELD32(0xff000000)/* * QOS_CSR1: TXOP holder MAC address register. */#define QOS_CSR1			0x30e4#define QOS_CSR1_BYTE4			FIELD32(0x000000ff)#define QOS_CSR1_BYTE5			FIELD32(0x0000ff00)/* * QOS_CSR2: TXOP holder timeout register. */#define QOS_CSR2			0x30e8/* * RX QOS-CFPOLL MAC address register. * QOS_CSR3: RX QOS-CFPOLL MAC address 0. * QOS_CSR4: RX QOS-CFPOLL MAC address 1. */#define QOS_CSR3			0x30ec#define QOS_CSR4			0x30f0/* * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL. */#define QOS_CSR5			0x30f4/* * Host DMA registers. *//* * AC0_BASE_CSR: AC_BK base address. */#define AC0_BASE_CSR			0x3400#define AC0_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)/* * AC1_BASE_CSR: AC_BE base address. */#define AC1_BASE_CSR			0x3404#define AC1_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)/* * AC2_BASE_CSR: AC_VI base address. */#define AC2_BASE_CSR			0x3408#define AC2_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)/* * AC3_BASE_CSR: AC_VO base address. */#define AC3_BASE_CSR			0x340c#define AC3_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)/* * MGMT_BASE_CSR: MGMT ring base address. */#define MGMT_BASE_CSR			0x3410#define MGMT_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)/* * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO. */#define TX_RING_CSR0			0x3418#define TX_RING_CSR0_AC0_RING_SIZE	FIELD32(0x000000ff)#define TX_RING_CSR0_AC1_RING_SIZE	FIELD32(0x0000ff00)#define TX_RING_CSR0_AC2_RING_SIZE	FIELD32(0x00ff0000)#define TX_RING_CSR0_AC3_RING_SIZE	FIELD32(0xff000000)/* * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring * TXD_SIZE: In unit of 32-bit. */#define TX_RING_CSR1			0x341c#define TX_RING_CSR1_MGMT_RING_SIZE	FIELD32(0x000000ff)#define TX_RING_CSR1_HCCA_RING_SIZE	FIELD32(0x0000ff00)#define TX_RING_CSR1_TXD_SIZE		FIELD32(0x003f0000)/* * AIFSN_CSR: AIFSN for each EDCA AC. * AIFSN0: For AC_BK. * AIFSN1: For AC_BE. * AIFSN2: For AC_VI. * AIFSN3: For AC_VO. */#define AIFSN_CSR			0x3420#define AIFSN_CSR_AIFSN0		FIELD32(0x0000000f)#define AIFSN_CSR_AIFSN1		FIELD32(0x000000f0)#define AIFSN_CSR_AIFSN2		FIELD32(0x00000f00)#define AIFSN_CSR_AIFSN3		FIELD32(0x0000f000)/* * CWMIN_CSR: CWmin for each EDCA AC. * CWMIN0: For AC_BK. * CWMIN1: For AC_BE. * CWMIN2: For AC_VI. * CWMIN3: For AC_VO. */#define CWMIN_CSR			0x3424#define CWMIN_CSR_CWMIN0		FIELD32(0x0000000f)#define CWMIN_CSR_CWMIN1		FIELD32(0x000000f0)#define CWMIN_CSR_CWMIN2		FIELD32(0x00000f00)#define CWMIN_CSR_CWMIN3		FIELD32(0x0000f000)/* * CWMAX_CSR: CWmax for each EDCA AC. * CWMAX0: For AC_BK. * CWMAX1: For AC_BE. * CWMAX2: For AC_VI. * CWMAX3: For AC_VO. */#define CWMAX_CSR			0x3428#define CWMAX_CSR_CWMAX0		FIELD32(0x0000000f)#define CWMAX_CSR_CWMAX1		FIELD32(0x000000f0)#define CWMAX_CSR_CWMAX2		FIELD32(0x00000f00)#define CWMAX_CSR_CWMAX3		FIELD32(0x0000f000)/* * TX_DMA_DST_CSR: TX DMA destination * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid */#define TX_DMA_DST_CSR			0x342c#define TX_DMA_DST_CSR_DEST_AC0		FIELD32(0x00000003)#define TX_DMA_DST_CSR_DEST_AC1		FIELD32(0x0000000c)#define TX_DMA_DST_CSR_DEST_AC2		FIELD32(0x00000030)#define TX_DMA_DST_CSR_DEST_AC3		FIELD32(0x000000c0)#define TX_DMA_DST_CSR_DEST_MGMT	FIELD32(0x00000300)/* * TX_CNTL_CSR: KICK/Abort TX. * KICK_TX_AC0: For AC_BK. * KICK_TX_AC1: For AC_BE. * KICK_TX_AC2: For AC_VI. * KICK_TX_AC3: For AC_VO. * ABORT_TX_AC0: For AC_BK. * ABORT_TX_AC1: For AC_BE. * ABORT_TX_AC2: For AC_VI. * ABORT_TX_AC3: For AC_VO. */#define TX_CNTL_CSR			0x3430#define TX_CNTL_CSR_KICK_TX_AC0		FIELD32(0x00000001)#define TX_CNTL_CSR_KICK_TX_AC1		FIELD32(0x00000002)#define TX_CNTL_CSR_KICK_TX_AC2		FIELD32(0x00000004)#define TX_CNTL_CSR_KICK_TX_AC3		FIELD32(0x00000008)#define TX_CNTL_CSR_KICK_TX_MGMT	FIELD32(0x00000010)#define TX_CNTL_CSR_ABORT_TX_AC0	FIELD32(0x00010000)#define TX_CNTL_CSR_ABORT_TX_AC1	FIELD32(0x00020000)#define TX_CNTL_CSR_ABORT_TX_AC2	FIELD32(0x00040000)#define TX_CNTL_CSR_ABORT_TX_AC3	FIELD32(0x00080000)#define TX_CNTL_CSR_ABORT_TX_MGMT	FIELD32(0x00100000)/* * LOAD_TX_RING_CSR: Load RX de */#define LOAD_TX_RING_CSR		0x3434#define LOAD_TX_RING_CSR_LOAD_TXD_AC0	FIELD32(0x00000001)#define LOAD_TX_RING_CSR_LOAD_TXD_AC1	FIELD32(0x00000002)#define LOAD_TX_RING_CSR_LOAD_TXD_AC2	FIELD32(0x00000004)#define LOAD_TX_RING_CSR_LOAD_TXD_AC3	FIELD32(0x00000008)#define LOAD_TX_RING_CSR_LOAD_TXD_MGMT	FIELD32(0x00000010)/* * Several read-only registers, for debugging. */#define AC0_TXPTR_CSR			0x3438#define AC1_TXPTR_CSR			0x343c#define AC2_TXPTR_CSR			0x3440#define AC3_TXPTR_CSR			0x3444#define MGMT_TXPTR_CSR			0x3448/* * RX_BASE_CSR */#define RX_BASE_CSR			0x3450#define RX_BASE_CSR_RING_REGISTER	FIELD32(0xffffffff)/* * RX_RING_CSR. * RXD_SIZE: In unit of 32-bit. */#define RX_RING_CSR			0x3454#define RX_RING_CSR_RING_SIZE		FIELD32(0x000000ff)#define RX_RING_CSR_RXD_SIZE		FIELD32(0x00003f00)#define RX_RING_CSR_RXD_WRITEBACK_SIZE	FIELD32(0x00070000)/* * RX_CNTL_CSR */#define RX_CNTL_CSR			0x3458#define RX_CNTL_CSR_ENABLE_RX_DMA	FIELD32(0x00000001)#define RX_CNTL_CSR_LOAD_RXD		FIELD32(0x00000002)/* * RXPTR_CSR: Read-only, for debugging. */#define RXPTR_CSR			0x345c/* * PCI_CFG_CSR */#define PCI_CFG_CSR			0x3460/* * BUF_FORMAT_CSR */#define BUF_FORMAT_CSR			0x3464/* * INT_SOURCE_CSR: Interrupt source register. * Write one to clear corresponding bit. */#define INT_SOURCE_CSR			0x3468#define INT_SOURCE_CSR_TXDONE		FIELD32(0x00000001)#define INT_SOURCE_CSR_RXDONE		FIELD32(0x00000002)#define INT_SOURCE_CSR_BEACON_DONE	FIELD32(0x00000004)#define INT_SOURCE_CSR_TX_ABORT_DONE	FIELD32(0x00000010)#define INT_SOURCE_CSR_AC0_DMA_DONE	FIELD32(0x00010000)#define INT_SOURCE_CSR_AC1_DMA_DONE	FIELD32(0x00020000)#define INT_SOURCE_CSR_AC2_DMA_DONE	FIELD32(0x00040000)#define INT_SOURCE_CSR_AC3_DMA_DONE	FIELD32(0x00080000)#define INT_SOURCE_CSR_MGMT_DMA_DONE	FIELD32(0x00100000)#define INT_SOURCE_CSR_HCCA_DMA_DONE	FIELD32(0x00200000)/* * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock. */#define INT_MASK_CSR			0x346c#define INT_MASK_CSR_TXDONE		FIELD32(0x00000001)#define INT_MASK_CSR_RXDONE		FIELD32(0x00000002)#define INT_MASK_CSR_BEACON_DONE	FIELD32(0x00000004)#define INT_MASK_CSR_TX_ABORT_DONE	FIELD32(0x00000010)#define INT_MASK_CSR_ENABLE_MITIGATION	FIELD32(0x00000080)#define INT_MASK_CSR_MITIGATION_PERIOD	FIELD32(0x0000ff00)#define INT_MASK_CSR_AC0_DMA_DONE	FIELD32(0x00010000)#define INT_MASK_CSR_AC1_DMA_DONE	FIELD32(0x00020000)#define INT_MASK_CSR_AC2_DMA_DONE	FIELD32(0x00040000)#define INT_MASK_CSR_AC3_DMA_DONE	FIELD32(0x00080000)#define INT_MASK_CSR_MGMT_DMA_DONE	FIELD32(0x00100000)#define INT_MASK_CSR_HCCA_DMA_DONE	FIELD32(0x00200000)/* * E2PROM_CSR: EEPROM control register. * RELOAD: Write 1 to reload eeprom content. * TYPE_93C46: 1: 93c46, 0:93c66. * LOAD_STATUS: 1:loading, 0:done. */#define E2PROM_CSR			0x3470#define E2PROM_CSR_RELOAD		FIELD32(0x00000001)#define E2PROM_CSR_DATA_CLOCK		FIELD32(0x00000002)#define E2PROM_CSR_CHIP_SELECT		FIELD32(0x00000004)#define E2PROM_CSR_DATA_IN		FIELD32(0x00000008)#define E2PROM_CSR_DATA_OUT		FIELD32(0x00000010)#define E2PROM_CSR_TYPE_93C46		FIELD32(0x00000020)#define E2PROM_CSR_LOAD_STATUS		FIELD32(0x00000040)
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