rt2400pci.h

linux内核源码

#define PCICSR_ENABLE_CLK		FIELD32(0x00000080)

/*
 * CNT0: FCS error count.
 * FCS_ERROR: FCS error count, cleared when read.
 */
#define CNT0				0x00a0
#define CNT0_FCS_ERROR			FIELD32(0x0000ffff)

/*
 * Statistic Register.
 * CNT1: PLCP error count.
 * CNT2: Long error count.
 * CNT3: CCA false alarm count.
 * CNT4: Rx FIFO overflow count.
 * CNT5: Tx FIFO underrun count.
 */
#define TIMECSR2			0x00a8
#define CNT1				0x00ac
#define CNT2				0x00b0
#define TIMECSR3			0x00b4
#define CNT3				0x00b8
#define CNT4				0x00bc
#define CNT5				0x00c0

/*
 * Baseband Control Register.
 */

/*
 * PWRCSR0: Power mode configuration register.
 */
#define PWRCSR0				0x00c4

/*
 * Power state transition time registers.
 */
#define PSCSR0				0x00c8
#define PSCSR1				0x00cc
#define PSCSR2				0x00d0
#define PSCSR3				0x00d4

/*
 * PWRCSR1: Manual power control / status register.
 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
 * SET_STATE: Set state. Write 1 to trigger, self cleared.
 * BBP_DESIRE_STATE: BBP desired state.
 * RF_DESIRE_STATE: RF desired state.
 * BBP_CURR_STATE: BBP current state.
 * RF_CURR_STATE: RF current state.
 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
 */
#define PWRCSR1				0x00d8
#define PWRCSR1_SET_STATE		FIELD32(0x00000001)
#define PWRCSR1_BBP_DESIRE_STATE	FIELD32(0x00000006)
#define PWRCSR1_RF_DESIRE_STATE		FIELD32(0x00000018)
#define PWRCSR1_BBP_CURR_STATE		FIELD32(0x00000060)
#define PWRCSR1_RF_CURR_STATE		FIELD32(0x00000180)
#define PWRCSR1_PUT_TO_SLEEP		FIELD32(0x00000200)

/*
 * TIMECSR: Timer control register.
 * US_COUNT: 1 us timer count in units of clock cycles.
 * US_64_COUNT: 64 us timer count in units of 1 us timer.
 * BEACON_EXPECT: Beacon expect window.
 */
#define TIMECSR				0x00dc
#define TIMECSR_US_COUNT		FIELD32(0x000000ff)
#define TIMECSR_US_64_COUNT		FIELD32(0x0000ff00)
#define TIMECSR_BEACON_EXPECT		FIELD32(0x00070000)

/*
 * MACCSR0: MAC configuration register 0.
 */
#define MACCSR0				0x00e0

/*
 * MACCSR1: MAC configuration register 1.
 * KICK_RX: Kick one-shot rx in one-shot rx mode.
 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
 * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
 * AUTO_TXBBP: Auto tx logic access bbp control register.
 * AUTO_RXBBP: Auto rx logic access bbp control register.
 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
 * INTERSIL_IF: Intersil if calibration pin.
 */
#define MACCSR1				0x00e4
#define MACCSR1_KICK_RX			FIELD32(0x00000001)
#define MACCSR1_ONESHOT_RXMODE		FIELD32(0x00000002)
#define MACCSR1_BBPRX_RESET_MODE	FIELD32(0x00000004)
#define MACCSR1_AUTO_TXBBP		FIELD32(0x00000008)
#define MACCSR1_AUTO_RXBBP		FIELD32(0x00000010)
#define MACCSR1_LOOPBACK		FIELD32(0x00000060)
#define MACCSR1_INTERSIL_IF		FIELD32(0x00000080)

/*
 * RALINKCSR: Ralink Rx auto-reset BBCR.
 * AR_BBP_DATA#: Auto reset BBP register # data.
 * AR_BBP_ID#: Auto reset BBP register # id.
 */
#define RALINKCSR			0x00e8
#define RALINKCSR_AR_BBP_DATA0		FIELD32(0x000000ff)
#define RALINKCSR_AR_BBP_ID0		FIELD32(0x0000ff00)
#define RALINKCSR_AR_BBP_DATA1		FIELD32(0x00ff0000)
#define RALINKCSR_AR_BBP_ID1		FIELD32(0xff000000)

/*
 * BCNCSR: Beacon interval control register.
 * CHANGE: Write one to change beacon interval.
 * DELTATIME: The delta time value.
 * NUM_BEACON: Number of beacon according to mode.
 * MODE: Please refer to asic specs.
 * PLUS: Plus or minus delta time value.
 */
#define BCNCSR				0x00ec
#define BCNCSR_CHANGE			FIELD32(0x00000001)
#define BCNCSR_DELTATIME		FIELD32(0x0000001e)
#define BCNCSR_NUM_BEACON		FIELD32(0x00001fe0)
#define BCNCSR_MODE			FIELD32(0x00006000)
#define BCNCSR_PLUS			FIELD32(0x00008000)

/*
 * BBP / RF / IF Control Register.
 */

/*
 * BBPCSR: BBP serial control register.
 * VALUE: Register value to program into BBP.
 * REGNUM: Selected BBP register.
 * BUSY: 1: asic is busy execute BBP programming.
 * WRITE_CONTROL: 1: write BBP, 0: read BBP.
 */
#define BBPCSR				0x00f0
#define BBPCSR_VALUE			FIELD32(0x000000ff)
#define BBPCSR_REGNUM			FIELD32(0x00007f00)
#define BBPCSR_BUSY			FIELD32(0x00008000)
#define BBPCSR_WRITE_CONTROL		FIELD32(0x00010000)

/*
 * RFCSR: RF serial control register.
 * VALUE: Register value + id to program into rf/if.
 * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
 * IF_SELECT: Chip to program: 0: rf, 1: if.
 * PLL_LD: Rf pll_ld status.
 * BUSY: 1: asic is busy execute rf programming.
 */
#define RFCSR				0x00f4
#define RFCSR_VALUE			FIELD32(0x00ffffff)
#define RFCSR_NUMBER_OF_BITS		FIELD32(0x1f000000)
#define RFCSR_IF_SELECT			FIELD32(0x20000000)
#define RFCSR_PLL_LD			FIELD32(0x40000000)
#define RFCSR_BUSY			FIELD32(0x80000000)

/*
 * LEDCSR: LED control register.
 * ON_PERIOD: On period, default 70ms.
 * OFF_PERIOD: Off period, default 30ms.
 * LINK: 0: linkoff, 1: linkup.
 * ACTIVITY: 0: idle, 1: active.
 */
#define LEDCSR				0x00f8
#define LEDCSR_ON_PERIOD		FIELD32(0x000000ff)
#define LEDCSR_OFF_PERIOD		FIELD32(0x0000ff00)
#define LEDCSR_LINK			FIELD32(0x00010000)
#define LEDCSR_ACTIVITY			FIELD32(0x00020000)

/*
 * ASIC pointer information.
 * RXPTR: Current RX ring address.
 * TXPTR: Current Tx ring address.
 * PRIPTR: Current Priority ring address.
 * ATIMPTR: Current ATIM ring address.
 */
#define RXPTR				0x0100
#define TXPTR				0x0104
#define PRIPTR				0x0108
#define ATIMPTR				0x010c

/*
 * GPIO and others.
 */

/*
 * GPIOCSR: GPIO control register.
 */
#define GPIOCSR				0x0120
#define GPIOCSR_BIT0			FIELD32(0x00000001)
#define GPIOCSR_BIT1			FIELD32(0x00000002)
#define GPIOCSR_BIT2			FIELD32(0x00000004)
#define GPIOCSR_BIT3			FIELD32(0x00000008)
#define GPIOCSR_BIT4			FIELD32(0x00000010)
#define GPIOCSR_BIT5			FIELD32(0x00000020)
#define GPIOCSR_BIT6			FIELD32(0x00000040)
#define GPIOCSR_BIT7			FIELD32(0x00000080)

/*
 * BBPPCSR: BBP Pin control register.
 */
#define BBPPCSR				0x0124

/*
 * BCNCSR1: Tx BEACON offset time control register.
 * PRELOAD: Beacon timer offset in units of usec.
 */
#define BCNCSR1				0x0130
#define BCNCSR1_PRELOAD			FIELD32(0x0000ffff)

/*
 * MACCSR2: TX_PE to RX_PE turn-around time control register
 * DELAY: RX_PE low width, in units of pci clock cycle.
 */
#define MACCSR2				0x0134
#define MACCSR2_DELAY			FIELD32(0x000000ff)

/*
 * ARCSR2: 1 Mbps ACK/CTS PLCP.
 */
#define ARCSR2				0x013c
#define ARCSR2_SIGNAL			FIELD32(0x000000ff)
#define ARCSR2_SERVICE			FIELD32(0x0000ff00)
#define ARCSR2_LENGTH_LOW		FIELD32(0x00ff0000)
#define ARCSR2_LENGTH			FIELD32(0xffff0000)

/*
 * ARCSR3: 2 Mbps ACK/CTS PLCP.
 */
#define ARCSR3				0x0140
#define ARCSR3_SIGNAL			FIELD32(0x000000ff)
#define ARCSR3_SERVICE			FIELD32(0x0000ff00)
#define ARCSR3_LENGTH			FIELD32(0xffff0000)

/*
 * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
 */
#define ARCSR4				0x0144
#define ARCSR4_SIGNAL			FIELD32(0x000000ff)
#define ARCSR4_SERVICE			FIELD32(0x0000ff00)
#define ARCSR4_LENGTH			FIELD32(0xffff0000)

/*
 * ARCSR5: 11 Mbps ACK/CTS PLCP.
 */
#define ARCSR5				0x0148
#define ARCSR5_SIGNAL			FIELD32(0x000000ff)
#define ARCSR5_SERVICE			FIELD32(0x0000ff00)
#define ARCSR5_LENGTH			FIELD32(0xffff0000)

/*
 * BBP registers.
 * The wordsize of the BBP is 8 bits.
 */

/*
 * R1: TX antenna control
 */
#define BBP_R1_TX_ANTENNA		FIELD8(0x03)

/*
 * R4: RX antenna control
 */
#define BBP_R4_RX_ANTENNA		FIELD8(0x06)

/*
 * RF registers
 */

/*
 * RF 1
 */
#define RF1_TUNER			FIELD32(0x00020000)

/*
 * RF 3
 */
#define RF3_TUNER			FIELD32(0x00000100)
#define RF3_TXPOWER			FIELD32(0x00003e00)

/*
 * EEPROM content.
 * The wordsize of the EEPROM is 16 bits.
 */

/*
 * HW MAC address.
 */
#define EEPROM_MAC_ADDR_0		0x0002
#define EEPROM_MAC_ADDR_BYTE0		FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE1		FIELD16(0xff00)
#define EEPROM_MAC_ADDR1		0x0003
#define EEPROM_MAC_ADDR_BYTE2		FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE3		FIELD16(0xff00)
#define EEPROM_MAC_ADDR_2		0x0004
#define EEPROM_MAC_ADDR_BYTE4		FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE5		FIELD16(0xff00)

/*
 * EEPROM antenna.
 * ANTENNA_NUM: Number of antenna's.
 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 * RF_TYPE: Rf_type of this adapter.
 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
 * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
 */
#define EEPROM_ANTENNA			0x0b
#define EEPROM_ANTENNA_NUM		FIELD16(0x0003)
#define EEPROM_ANTENNA_TX_DEFAULT	FIELD16(0x000c)
#define EEPROM_ANTENNA_RX_DEFAULT	FIELD16(0x0030)
#define EEPROM_ANTENNA_RF_TYPE		FIELD16(0x0040)
#define EEPROM_ANTENNA_LED_MODE		FIELD16(0x0180)
#define EEPROM_ANTENNA_RX_AGCVGC_TUNING	FIELD16(0x0200)
#define EEPROM_ANTENNA_HARDWARE_RADIO	FIELD16(0x0400)

/*
 * EEPROM BBP.
 */
#define EEPROM_BBP_START		0x0c
#define EEPROM_BBP_SIZE			7
#define EEPROM_BBP_VALUE		FIELD16(0x00ff)
#define EEPROM_BBP_REG_ID		FIELD16(0xff00)

/*
 * EEPROM TXPOWER
 */
#define EEPROM_TXPOWER_START		0x13
#define EEPROM_TXPOWER_SIZE		7
#define EEPROM_TXPOWER_1		FIELD16(0x00ff)
#define EEPROM_TXPOWER_2		FIELD16(0xff00)

/*
 * DMA descriptor defines.
 */
#define TXD_DESC_SIZE			( 8 * sizeof(struct data_desc) )
#define RXD_DESC_SIZE			( 8 * sizeof(struct data_desc) )

/*
 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
 */

/*
 * Word0
 */
#define TXD_W0_OWNER_NIC		FIELD32(0x00000001)
#define TXD_W0_VALID			FIELD32(0x00000002)
#define TXD_W0_RESULT			FIELD32(0x0000001c)
#define TXD_W0_RETRY_COUNT		FIELD32(0x000000e0)
#define TXD_W0_MORE_FRAG		FIELD32(0x00000100)
#define TXD_W0_ACK			FIELD32(0x00000200)
#define TXD_W0_TIMESTAMP		FIELD32(0x00000400)
#define TXD_W0_RTS			FIELD32(0x00000800)
#define TXD_W0_IFS			FIELD32(0x00006000)
#define TXD_W0_RETRY_MODE		FIELD32(0x00008000)
#define TXD_W0_AGC			FIELD32(0x00ff0000)
#define TXD_W0_R2			FIELD32(0xff000000)

/*
 * Word1
 */
#define TXD_W1_BUFFER_ADDRESS		FIELD32(0xffffffff)

/*
 * Word2
 */
#define TXD_W2_BUFFER_LENGTH		FIELD32(0x0000ffff)
#define TXD_W2_DATABYTE_COUNT		FIELD32(0xffff0000)

/*
 * Word3 & 4: PLCP information
 */
#define TXD_W3_PLCP_SIGNAL		FIELD32(0x0000ffff)
#define TXD_W3_PLCP_SERVICE		FIELD32(0xffff0000)
#define TXD_W4_PLCP_LENGTH_LOW		FIELD32(0x0000ffff)
#define TXD_W4_PLCP_LENGTH_HIGH		FIELD32(0xffff0000)

/*
 * Word5
 */
#define TXD_W5_BBCR4			FIELD32(0x0000ffff)
#define TXD_W5_AGC_REG			FIELD32(0x007f0000)
#define TXD_W5_AGC_REG_VALID		FIELD32(0x00800000)
#define TXD_W5_XXX_REG			FIELD32(0x7f000000)
#define TXD_W5_XXX_REG_VALID		FIELD32(0x80000000)

/*
 * Word6
 */
#define TXD_W6_SK_BUFF			FIELD32(0xffffffff)

/*
 * Word7
 */
#define TXD_W7_RESERVED			FIELD32(0xffffffff)

/*
 * RX descriptor format for RX Ring.
 */

/*
 * Word0
 */
#define RXD_W0_OWNER_NIC		FIELD32(0x00000001)
#define RXD_W0_UNICAST_TO_ME		FIELD32(0x00000002)
#define RXD_W0_MULTICAST		FIELD32(0x00000004)
#define RXD_W0_BROADCAST		FIELD32(0x00000008)
#define RXD_W0_MY_BSS			FIELD32(0x00000010)
#define RXD_W0_CRC_ERROR		FIELD32(0x00000020)
#define RXD_W0_PHYSICAL_ERROR		FIELD32(0x00000080)
#define RXD_W0_DATABYTE_COUNT		FIELD32(0xffff0000)

/*
 * Word1
 */
#define RXD_W1_BUFFER_ADDRESS		FIELD32(0xffffffff)

/*
 * Word2
 */
#define RXD_W2_BUFFER_LENGTH		FIELD32(0x0000ffff)
#define RXD_W2_SIGNAL			FIELD32(0x00ff0000)
#define RXD_W2_RSSI			FIELD32(0xff000000)

/*
 * Word3
 */
#define RXD_W3_BBR2			FIELD32(0x000000ff)
#define RXD_W3_BBR3			FIELD32(0x0000ff00)
#define RXD_W3_BBR4			FIELD32(0x00ff0000)
#define RXD_W3_BBR5			FIELD32(0xff000000)

/*
 * Word4
 */
#define RXD_W4_RX_END_TIME		FIELD32(0xffffffff)

/*
 * Word5 & 6 & 7: Reserved
 */
#define RXD_W5_RESERVED			FIELD32(0xffffffff)
#define RXD_W6_RESERVED			FIELD32(0xffffffff)
#define RXD_W7_RESERVED			FIELD32(0xffffffff)

/*
 * Macro's for converting txpower from EEPROM to dscape value
 * and from dscape value to register value.
 * NOTE: Logics in rt2400pci for txpower are reversed
 * compared to the other rt2x00 drivers. A higher txpower
 * value means that the txpower must be lowered. This is
 * important when converting the value coming from the
 * dscape stack to the rt2400 acceptable value.
 */
#define MIN_TXPOWER	31
#define MAX_TXPOWER	62
#define DEFAULT_TXPOWER	39

#define TXPOWER_FROM_DEV(__txpower)					\
({									\
	((__txpower) > MAX_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER :	\
	((__txpower) < MIN_TXPOWER) ? DEFAULT_TXPOWER - MIN_TXPOWER :	\
	(((__txpower) - MAX_TXPOWER) + MIN_TXPOWER);			\
})

#define TXPOWER_TO_DEV(__txpower)			\
({							\
	(__txpower) += MIN_TXPOWER;			\
	((__txpower) <= MIN_TXPOWER) ? MAX_TXPOWER :	\
	(((__txpower) >= MAX_TXPOWER) ? MIN_TXPOWER :	\
	(MAX_TXPOWER - ((__txpower) - MIN_TXPOWER)));	\
})

#endif /* RT2400PCI_H */