rt2500usb.h

linux内核源码

#define SEC_CSR21			0x04aa
#define SEC_CSR22			0x04ac
#define SEC_CSR23			0x04ae

/*
 * SEC_CSR24-SEC_CSR31: Shared key 3, word 0-7
 */
#define SEC_CSR24			0x04b0
#define SEC_CSR25			0x04b2
#define SEC_CSR26			0x04b4
#define SEC_CSR27			0x04b6
#define SEC_CSR28			0x04b8
#define SEC_CSR29			0x04ba
#define SEC_CSR30			0x04bc
#define SEC_CSR31			0x04be

/*
 * PHY control registers.
 */

/*
 * PHY_CSR0: RF switching timing control.
 */
#define PHY_CSR0			0x04c0

/*
 * PHY_CSR1: TX PA configuration.
 */
#define PHY_CSR1			0x04c2

/*
 * MAC configuration registers.
 * PHY_CSR2: TX MAC configuration.
 * PHY_CSR3: RX MAC configuration.
 */
#define PHY_CSR2			0x04c4
#define PHY_CSR3			0x04c6

/*
 * PHY_CSR4: Interface configuration.
 */
#define PHY_CSR4			0x04c8
#define PHY_CSR4_LOW_RF_LE		FIELD16(0x0001)

/*
 * BBP pre-TX registers.
 * PHY_CSR5: BBP pre-TX CCK.
 */
#define PHY_CSR5			0x04ca
#define PHY_CSR5_CCK			FIELD16(0x0003)
#define PHY_CSR5_CCK_FLIP		FIELD16(0x0004)

/*
 * BBP pre-TX registers.
 * PHY_CSR6: BBP pre-TX OFDM.
 */
#define PHY_CSR6			0x04cc
#define PHY_CSR6_OFDM			FIELD16(0x0003)
#define PHY_CSR6_OFDM_FLIP		FIELD16(0x0004)

/*
 * PHY_CSR7: BBP access register 0.
 * BBP_DATA: BBP data.
 * BBP_REG_ID: BBP register ID.
 * BBP_READ_CONTROL: 0: write, 1: read.
 */
#define PHY_CSR7			0x04ce
#define PHY_CSR7_DATA			FIELD16(0x00ff)
#define PHY_CSR7_REG_ID			FIELD16(0x7f00)
#define PHY_CSR7_READ_CONTROL		FIELD16(0x8000)

/*
 * PHY_CSR8: BBP access register 1.
 * BBP_BUSY: ASIC is busy execute BBP programming.
 */
#define PHY_CSR8			0x04d0
#define PHY_CSR8_BUSY			FIELD16(0x0001)

/*
 * PHY_CSR9: RF access register.
 * RF_VALUE: Register value + id to program into rf/if.
 */
#define PHY_CSR9			0x04d2
#define PHY_CSR9_RF_VALUE		FIELD16(0xffff)

/*
 * PHY_CSR10: RF access register.
 * RF_VALUE: Register value + id to program into rf/if.
 * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
 * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
 * RF_PLL_LD: Rf pll_ld status.
 * RF_BUSY: 1: asic is busy execute rf programming.
 */
#define PHY_CSR10			0x04d4
#define PHY_CSR10_RF_VALUE		FIELD16(0x00ff)
#define PHY_CSR10_RF_NUMBER_OF_BITS	FIELD16(0x1f00)
#define PHY_CSR10_RF_IF_SELECT		FIELD16(0x2000)
#define PHY_CSR10_RF_PLL_LD		FIELD16(0x4000)
#define PHY_CSR10_RF_BUSY		FIELD16(0x8000)

/*
 * STA_CSR0: FCS error count.
 * FCS_ERROR: FCS error count, cleared when read.
 */
#define STA_CSR0			0x04e0
#define STA_CSR0_FCS_ERROR		FIELD16(0xffff)

/*
 * STA_CSR1: PLCP error count.
 */
#define STA_CSR1			0x04e2

/*
 * STA_CSR2: LONG error count.
 */
#define STA_CSR2			0x04e4

/*
 * STA_CSR3: CCA false alarm.
 * FALSE_CCA_ERROR: False CCA error count, cleared when read.
 */
#define STA_CSR3			0x04e6
#define STA_CSR3_FALSE_CCA_ERROR	FIELD16(0xffff)

/*
 * STA_CSR4: RX FIFO overflow.
 */
#define STA_CSR4			0x04e8

/*
 * STA_CSR5: Beacon sent counter.
 */
#define STA_CSR5			0x04ea

/*
 *  Statistics registers
 */
#define STA_CSR6			0x04ec
#define STA_CSR7			0x04ee
#define STA_CSR8			0x04f0
#define STA_CSR9			0x04f2
#define STA_CSR10			0x04f4

/*
 * BBP registers.
 * The wordsize of the BBP is 8 bits.
 */

/*
 * R2: TX antenna control
 */
#define BBP_R2_TX_ANTENNA		FIELD8(0x03)
#define BBP_R2_TX_IQ_FLIP		FIELD8(0x04)

/*
 * R14: RX antenna control
 */
#define BBP_R14_RX_ANTENNA		FIELD8(0x03)
#define BBP_R14_RX_IQ_FLIP		FIELD8(0x04)

/*
 * RF registers.
 */

/*
 * RF 1
 */
#define RF1_TUNER			FIELD32(0x00020000)

/*
 * RF 3
 */
#define RF3_TUNER			FIELD32(0x00000100)
#define RF3_TXPOWER			FIELD32(0x00003e00)

/*
 * EEPROM contents.
 */

/*
 * HW MAC address.
 */
#define EEPROM_MAC_ADDR_0		0x0002
#define EEPROM_MAC_ADDR_BYTE0		FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE1		FIELD16(0xff00)
#define EEPROM_MAC_ADDR1		0x0003
#define EEPROM_MAC_ADDR_BYTE2		FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE3		FIELD16(0xff00)
#define EEPROM_MAC_ADDR_2		0x0004
#define EEPROM_MAC_ADDR_BYTE4		FIELD16(0x00ff)
#define EEPROM_MAC_ADDR_BYTE5		FIELD16(0xff00)

/*
 * EEPROM antenna.
 * ANTENNA_NUM: Number of antenna's.
 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
 * DYN_TXAGC: Dynamic TX AGC control.
 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
 * RF_TYPE: Rf_type of this adapter.
 */
#define EEPROM_ANTENNA			0x000b
#define EEPROM_ANTENNA_NUM		FIELD16(0x0003)
#define EEPROM_ANTENNA_TX_DEFAULT	FIELD16(0x000c)
#define EEPROM_ANTENNA_RX_DEFAULT	FIELD16(0x0030)
#define EEPROM_ANTENNA_LED_MODE		FIELD16(0x01c0)
#define EEPROM_ANTENNA_DYN_TXAGC	FIELD16(0x0200)
#define EEPROM_ANTENNA_HARDWARE_RADIO	FIELD16(0x0400)
#define EEPROM_ANTENNA_RF_TYPE		FIELD16(0xf800)

/*
 * EEPROM NIC config.
 * CARDBUS_ACCEL: 0: enable, 1: disable.
 * DYN_BBP_TUNE: 0: enable, 1: disable.
 * CCK_TX_POWER: CCK TX power compensation.
 */
#define EEPROM_NIC			0x000c
#define EEPROM_NIC_CARDBUS_ACCEL	FIELD16(0x0001)
#define EEPROM_NIC_DYN_BBP_TUNE		FIELD16(0x0002)
#define EEPROM_NIC_CCK_TX_POWER		FIELD16(0x000c)

/*
 * EEPROM geography.
 * GEO: Default geography setting for device.
 */
#define EEPROM_GEOGRAPHY		0x000d
#define EEPROM_GEOGRAPHY_GEO		FIELD16(0x0f00)

/*
 * EEPROM BBP.
 */
#define EEPROM_BBP_START		0x000e
#define EEPROM_BBP_SIZE			16
#define EEPROM_BBP_VALUE		FIELD16(0x00ff)
#define EEPROM_BBP_REG_ID		FIELD16(0xff00)

/*
 * EEPROM TXPOWER
 */
#define EEPROM_TXPOWER_START		0x001e
#define EEPROM_TXPOWER_SIZE		7
#define EEPROM_TXPOWER_1		FIELD16(0x00ff)
#define EEPROM_TXPOWER_2		FIELD16(0xff00)

/*
 * EEPROM Tuning threshold
 */
#define EEPROM_BBPTUNE			0x0030
#define EEPROM_BBPTUNE_THRESHOLD	FIELD16(0x00ff)

/*
 * EEPROM BBP R24 Tuning.
 */
#define EEPROM_BBPTUNE_R24		0x0031
#define EEPROM_BBPTUNE_R24_LOW		FIELD16(0x00ff)
#define EEPROM_BBPTUNE_R24_HIGH		FIELD16(0xff00)

/*
 * EEPROM BBP R25 Tuning.
 */
#define EEPROM_BBPTUNE_R25		0x0032
#define EEPROM_BBPTUNE_R25_LOW		FIELD16(0x00ff)
#define EEPROM_BBPTUNE_R25_HIGH		FIELD16(0xff00)

/*
 * EEPROM BBP R24 Tuning.
 */
#define EEPROM_BBPTUNE_R61		0x0033
#define EEPROM_BBPTUNE_R61_LOW		FIELD16(0x00ff)
#define EEPROM_BBPTUNE_R61_HIGH		FIELD16(0xff00)

/*
 * EEPROM BBP VGC Tuning.
 */
#define EEPROM_BBPTUNE_VGC		0x0034
#define EEPROM_BBPTUNE_VGCUPPER		FIELD16(0x00ff)

/*
 * EEPROM BBP R17 Tuning.
 */
#define EEPROM_BBPTUNE_R17		0x0035
#define EEPROM_BBPTUNE_R17_LOW		FIELD16(0x00ff)
#define EEPROM_BBPTUNE_R17_HIGH		FIELD16(0xff00)

/*
 * RSSI <-> dBm offset calibration
 */
#define EEPROM_CALIBRATE_OFFSET		0x0036
#define EEPROM_CALIBRATE_OFFSET_RSSI	FIELD16(0x00ff)

/*
 * DMA descriptor defines.
 */
#define TXD_DESC_SIZE			( 5 * sizeof(struct data_desc) )
#define RXD_DESC_SIZE			( 4 * sizeof(struct data_desc) )

/*
 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
 */

/*
 * Word0
 */
#define TXD_W0_PACKET_ID		FIELD32(0x0000000f)
#define TXD_W0_RETRY_LIMIT		FIELD32(0x000000f0)
#define TXD_W0_MORE_FRAG		FIELD32(0x00000100)
#define TXD_W0_ACK			FIELD32(0x00000200)
#define TXD_W0_TIMESTAMP		FIELD32(0x00000400)
#define TXD_W0_OFDM			FIELD32(0x00000800)
#define TXD_W0_NEW_SEQ			FIELD32(0x00001000)
#define TXD_W0_IFS			FIELD32(0x00006000)
#define TXD_W0_DATABYTE_COUNT		FIELD32(0x0fff0000)
#define TXD_W0_CIPHER			FIELD32(0x20000000)
#define TXD_W0_KEY_ID			FIELD32(0xc0000000)

/*
 * Word1
 */
#define TXD_W1_IV_OFFSET		FIELD32(0x0000003f)
#define TXD_W1_AIFS			FIELD32(0x000000c0)
#define TXD_W1_CWMIN			FIELD32(0x00000f00)
#define TXD_W1_CWMAX			FIELD32(0x0000f000)

/*
 * Word2: PLCP information
 */
#define TXD_W2_PLCP_SIGNAL		FIELD32(0x000000ff)
#define TXD_W2_PLCP_SERVICE		FIELD32(0x0000ff00)
#define TXD_W2_PLCP_LENGTH_LOW		FIELD32(0x00ff0000)
#define TXD_W2_PLCP_LENGTH_HIGH		FIELD32(0xff000000)

/*
 * Word3
 */
#define TXD_W3_IV			FIELD32(0xffffffff)

/*
 * Word4
 */
#define TXD_W4_EIV			FIELD32(0xffffffff)

/*
 * RX descriptor format for RX Ring.
 */

/*
 * Word0
 */
#define RXD_W0_UNICAST_TO_ME		FIELD32(0x00000002)
#define RXD_W0_MULTICAST		FIELD32(0x00000004)
#define RXD_W0_BROADCAST		FIELD32(0x00000008)
#define RXD_W0_MY_BSS			FIELD32(0x00000010)
#define RXD_W0_CRC_ERROR		FIELD32(0x00000020)
#define RXD_W0_OFDM			FIELD32(0x00000040)
#define RXD_W0_PHYSICAL_ERROR		FIELD32(0x00000080)
#define RXD_W0_CIPHER			FIELD32(0x00000100)
#define RXD_W0_CIPHER_ERROR		FIELD32(0x00000200)
#define RXD_W0_DATABYTE_COUNT		FIELD32(0x0fff0000)

/*
 * Word1
 */
#define RXD_W1_RSSI			FIELD32(0x000000ff)
#define RXD_W1_SIGNAL			FIELD32(0x0000ff00)

/*
 * Word2
 */
#define RXD_W2_IV			FIELD32(0xffffffff)

/*
 * Word3
 */
#define RXD_W3_EIV			FIELD32(0xffffffff)

/*
 * Macro's for converting txpower from EEPROM to dscape value
 * and from dscape value to register value.
 */
#define MIN_TXPOWER	0
#define MAX_TXPOWER	31
#define DEFAULT_TXPOWER	24

#define TXPOWER_FROM_DEV(__txpower)		\
({						\
	((__txpower) > MAX_TXPOWER) ?		\
		DEFAULT_TXPOWER : (__txpower);	\
})

#define TXPOWER_TO_DEV(__txpower)			\
({							\
	((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER :	\
	(((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER :	\
	(__txpower));					\
})

#endif /* RT2500USB_H */