rt2500usb.h

linux内核源码

/*
	Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
	<http://rt2x00.serialmonkey.com>

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the
	Free Software Foundation, Inc.,
	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/*
	Module: rt2500usb
	Abstract: Data structures and registers for the rt2500usb module.
	Supported chipsets: RT2570.
 */

#ifndef RT2500USB_H
#define RT2500USB_H

/*
 * RF chip defines.
 */
#define RF2522				0x0000
#define RF2523				0x0001
#define RF2524				0x0002
#define RF2525				0x0003
#define RF2525E				0x0005
#define RF5222				0x0010

/*
 * RT2570 version
 */
#define RT2570_VERSION_B		2
#define RT2570_VERSION_C		3
#define RT2570_VERSION_D		4

/*
 * Signal information.
 * Defaul offset is required for RSSI <-> dBm conversion.
 */
#define MAX_SIGNAL			100
#define MAX_RX_SSI			-1
#define DEFAULT_RSSI_OFFSET		120

/*
 * Register layout information.
 */
#define CSR_REG_BASE			0x0400
#define CSR_REG_SIZE			0x0100
#define EEPROM_BASE			0x0000
#define EEPROM_SIZE			0x006a
#define BBP_SIZE			0x0060
#define RF_SIZE				0x0014

/*
 * Control/Status Registers(CSR).
 * Some values are set in TU, whereas 1 TU == 1024 us.
 */

/*
 * MAC_CSR0: ASIC revision number.
 */
#define MAC_CSR0			0x0400

/*
 * MAC_CSR1: System control.
 * SOFT_RESET: Software reset, 1: reset, 0: normal.
 * BBP_RESET: Hardware reset, 1: reset, 0, release.
 * HOST_READY: Host ready after initialization.
 */
#define MAC_CSR1			0x0402
#define MAC_CSR1_SOFT_RESET		FIELD16(0x00000001)
#define MAC_CSR1_BBP_RESET		FIELD16(0x00000002)
#define MAC_CSR1_HOST_READY		FIELD16(0x00000004)

/*
 * MAC_CSR2: STA MAC register 0.
 */
#define MAC_CSR2			0x0404
#define MAC_CSR2_BYTE0			FIELD16(0x00ff)
#define MAC_CSR2_BYTE1			FIELD16(0xff00)

/*
 * MAC_CSR3: STA MAC register 1.
 */
#define MAC_CSR3			0x0406
#define MAC_CSR3_BYTE2			FIELD16(0x00ff)
#define MAC_CSR3_BYTE3			FIELD16(0xff00)

/*
 * MAC_CSR4: STA MAC register 2.
 */
#define MAC_CSR4			0X0408
#define MAC_CSR4_BYTE4			FIELD16(0x00ff)
#define MAC_CSR4_BYTE5			FIELD16(0xff00)

/*
 * MAC_CSR5: BSSID register 0.
 */
#define MAC_CSR5			0x040a
#define MAC_CSR5_BYTE0			FIELD16(0x00ff)
#define MAC_CSR5_BYTE1			FIELD16(0xff00)

/*
 * MAC_CSR6: BSSID register 1.
 */
#define MAC_CSR6			0x040c
#define MAC_CSR6_BYTE2			FIELD16(0x00ff)
#define MAC_CSR6_BYTE3			FIELD16(0xff00)

/*
 * MAC_CSR7: BSSID register 2.
 */
#define MAC_CSR7			0x040e
#define MAC_CSR7_BYTE4			FIELD16(0x00ff)
#define MAC_CSR7_BYTE5			FIELD16(0xff00)

/*
 * MAC_CSR8: Max frame length.
 */
#define MAC_CSR8			0x0410
#define MAC_CSR8_MAX_FRAME_UNIT		FIELD16(0x0fff)

/*
 * Misc MAC_CSR registers.
 * MAC_CSR9: Timer control.
 * MAC_CSR10: Slot time.
 * MAC_CSR11: IFS.
 * MAC_CSR12: EIFS.
 * MAC_CSR13: Power mode0.
 * MAC_CSR14: Power mode1.
 * MAC_CSR15: Power saving transition0
 * MAC_CSR16: Power saving transition1
 */
#define MAC_CSR9			0x0412
#define MAC_CSR10			0x0414
#define MAC_CSR11			0x0416
#define MAC_CSR12			0x0418
#define MAC_CSR13			0x041a
#define MAC_CSR14			0x041c
#define MAC_CSR15			0x041e
#define MAC_CSR16			0x0420

/*
 * MAC_CSR17: Manual power control / status register.
 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
 * SET_STATE: Set state. Write 1 to trigger, self cleared.
 * BBP_DESIRE_STATE: BBP desired state.
 * RF_DESIRE_STATE: RF desired state.
 * BBP_CURRENT_STATE: BBP current state.
 * RF_CURRENT_STATE: RF current state.
 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
 */
#define MAC_CSR17			0x0422
#define MAC_CSR17_SET_STATE		FIELD16(0x0001)
#define MAC_CSR17_BBP_DESIRE_STATE	FIELD16(0x0006)
#define MAC_CSR17_RF_DESIRE_STATE	FIELD16(0x0018)
#define MAC_CSR17_BBP_CURR_STATE	FIELD16(0x0060)
#define MAC_CSR17_RF_CURR_STATE		FIELD16(0x0180)
#define MAC_CSR17_PUT_TO_SLEEP		FIELD16(0x0200)

/*
 * MAC_CSR18: Wakeup timer register.
 * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
 * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
 * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
 */
#define MAC_CSR18			0x0424
#define MAC_CSR18_DELAY_AFTER_BEACON	FIELD16(0x00ff)
#define MAC_CSR18_BEACONS_BEFORE_WAKEUP	FIELD16(0x7f00)
#define MAC_CSR18_AUTO_WAKE		FIELD16(0x8000)

/*
 * MAC_CSR19: GPIO control register.
 */
#define MAC_CSR19			0x0426

/*
 * MAC_CSR20: LED control register.
 * ACTIVITY: 0: idle, 1: active.
 * LINK: 0: linkoff, 1: linkup.
 * ACTIVITY_POLARITY: 0: active low, 1: active high.
 */
#define MAC_CSR20			0x0428
#define MAC_CSR20_ACTIVITY		FIELD16(0x0001)
#define MAC_CSR20_LINK			FIELD16(0x0002)
#define MAC_CSR20_ACTIVITY_POLARITY	FIELD16(0x0004)

/*
 * MAC_CSR21: LED control register.
 * ON_PERIOD: On period, default 70ms.
 * OFF_PERIOD: Off period, default 30ms.
 */
#define MAC_CSR21			0x042a
#define MAC_CSR21_ON_PERIOD		FIELD16(0x00ff)
#define MAC_CSR21_OFF_PERIOD		FIELD16(0xff00)

/*
 * Collision window control register.
 */
#define MAC_CSR22			0x042c

/*
 * Transmit related CSRs.
 * Some values are set in TU, whereas 1 TU == 1024 us.
 */

/*
 * TXRX_CSR0: Security control register.
 */
#define TXRX_CSR0			0x0440
#define TXRX_CSR0_ALGORITHM		FIELD16(0x0007)
#define TXRX_CSR0_IV_OFFSET		FIELD16(0x01f8)
#define TXRX_CSR0_KEY_ID		FIELD16(0x1e00)

/*
 * TXRX_CSR1: TX configuration.
 * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
 * TSF_OFFSET: TSF offset in MAC header.
 * AUTO_SEQUENCE: Let ASIC control frame sequence number.
 */
#define TXRX_CSR1			0x0442
#define TXRX_CSR1_ACK_TIMEOUT		FIELD16(0x00ff)
#define TXRX_CSR1_TSF_OFFSET		FIELD16(0x7f00)
#define TXRX_CSR1_AUTO_SEQUENCE		FIELD16(0x8000)

/*
 * TXRX_CSR2: RX control.
 * DISABLE_RX: Disable rx engine.
 * DROP_CRC: Drop crc error.
 * DROP_PHYSICAL: Drop physical error.
 * DROP_CONTROL: Drop control frame.
 * DROP_NOT_TO_ME: Drop not to me unicast frame.
 * DROP_TODS: Drop frame tods bit is true.
 * DROP_VERSION_ERROR: Drop version error frame.
 * DROP_MCAST: Drop multicast frames.
 * DROP_BCAST: Drop broadcast frames.
 */
#define TXRX_CSR2			0x0444
#define	TXRX_CSR2_DISABLE_RX		FIELD16(0x0001)
#define TXRX_CSR2_DROP_CRC		FIELD16(0x0002)
#define TXRX_CSR2_DROP_PHYSICAL		FIELD16(0x0004)
#define TXRX_CSR2_DROP_CONTROL		FIELD16(0x0008)
#define TXRX_CSR2_DROP_NOT_TO_ME	FIELD16(0x0010)
#define TXRX_CSR2_DROP_TODS		FIELD16(0x0020)
#define TXRX_CSR2_DROP_VERSION_ERROR	FIELD16(0x0040)
#define TXRX_CSR2_DROP_MULTICAST	FIELD16(0x0200)
#define TXRX_CSR2_DROP_BROADCAST	FIELD16(0x0400)

/*
 * RX BBP ID registers
 * TXRX_CSR3: CCK RX BBP ID.
 * TXRX_CSR4: OFDM RX BBP ID.
 */
#define TXRX_CSR3			0x0446
#define TXRX_CSR4			0x0448

/*
 * TXRX_CSR5: CCK TX BBP ID0.
 */
#define TXRX_CSR5			0x044a
#define TXRX_CSR5_BBP_ID0		FIELD16(0x007f)
#define TXRX_CSR5_BBP_ID0_VALID		FIELD16(0x0080)
#define TXRX_CSR5_BBP_ID1		FIELD16(0x7f00)
#define TXRX_CSR5_BBP_ID1_VALID		FIELD16(0x8000)

/*
 * TXRX_CSR6: CCK TX BBP ID1.
 */
#define TXRX_CSR6			0x044c
#define TXRX_CSR6_BBP_ID0		FIELD16(0x007f)
#define TXRX_CSR6_BBP_ID0_VALID		FIELD16(0x0080)
#define TXRX_CSR6_BBP_ID1		FIELD16(0x7f00)
#define TXRX_CSR6_BBP_ID1_VALID		FIELD16(0x8000)

/*
 * TXRX_CSR7: OFDM TX BBP ID0.
 */
#define TXRX_CSR7			0x044e
#define TXRX_CSR7_BBP_ID0		FIELD16(0x007f)
#define TXRX_CSR7_BBP_ID0_VALID		FIELD16(0x0080)
#define TXRX_CSR7_BBP_ID1		FIELD16(0x7f00)
#define TXRX_CSR7_BBP_ID1_VALID		FIELD16(0x8000)

/*
 * TXRX_CSR5: OFDM TX BBP ID1.
 */
#define TXRX_CSR8			0x0450
#define TXRX_CSR8_BBP_ID0		FIELD16(0x007f)
#define TXRX_CSR8_BBP_ID0_VALID		FIELD16(0x0080)
#define TXRX_CSR8_BBP_ID1		FIELD16(0x7f00)
#define TXRX_CSR8_BBP_ID1_VALID		FIELD16(0x8000)

/*
 * TXRX_CSR9: TX ACK time-out.
 */
#define TXRX_CSR9			0x0452

/*
 * TXRX_CSR10: Auto responder control.
 */
#define TXRX_CSR10			0x0454
#define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)

/*
 * TXRX_CSR11: Auto responder basic rate.
 */
#define TXRX_CSR11			0x0456

/*
 * ACK/CTS time registers.
 */
#define TXRX_CSR12			0x0458
#define TXRX_CSR13			0x045a
#define TXRX_CSR14			0x045c
#define TXRX_CSR15			0x045e
#define TXRX_CSR16			0x0460
#define TXRX_CSR17			0x0462

/*
 * TXRX_CSR18: Synchronization control register.
 */
#define TXRX_CSR18			0x0464
#define TXRX_CSR18_OFFSET		FIELD16(0x000f)
#define TXRX_CSR18_INTERVAL		FIELD16(0xfff0)

/*
 * TXRX_CSR19: Synchronization control register.
 * TSF_COUNT: Enable TSF auto counting.
 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 * TBCN: Enable Tbcn with reload value.
 * BEACON_GEN: Enable beacon generator.
 */
#define TXRX_CSR19			0x0466
#define TXRX_CSR19_TSF_COUNT		FIELD16(0x0001)
#define TXRX_CSR19_TSF_SYNC		FIELD16(0x0006)
#define TXRX_CSR19_TBCN			FIELD16(0x0008)
#define TXRX_CSR19_BEACON_GEN		FIELD16(0x0010)

/*
 * TXRX_CSR20: Tx BEACON offset time control register.
 * OFFSET: In units of usec.
 * BCN_EXPECT_WINDOW: Default: 2^CWmin
 */
#define TXRX_CSR20			0x0468
#define TXRX_CSR20_OFFSET		FIELD16(0x1fff)
#define TXRX_CSR20_BCN_EXPECT_WINDOW	FIELD16(0xe000)

/*
 * TXRX_CSR21
 */
#define TXRX_CSR21			0x046a

/*
 * Encryption related CSRs.
 *
 */

/*
 * SEC_CSR0-SEC_CSR7: Shared key 0, word 0-7
 */
#define SEC_CSR0			0x0480
#define SEC_CSR1			0x0482
#define SEC_CSR2			0x0484
#define SEC_CSR3			0x0486
#define SEC_CSR4			0x0488
#define SEC_CSR5			0x048a
#define SEC_CSR6			0x048c
#define SEC_CSR7			0x048e

/*
 * SEC_CSR8-SEC_CSR15: Shared key 1, word 0-7
 */
#define SEC_CSR8			0x0490
#define SEC_CSR9			0x0492
#define SEC_CSR10			0x0494
#define SEC_CSR11			0x0496
#define SEC_CSR12			0x0498
#define SEC_CSR13			0x049a
#define SEC_CSR14			0x049c
#define SEC_CSR15			0x049e

/*
 * SEC_CSR16-SEC_CSR23: Shared key 2, word 0-7
 */
#define SEC_CSR16			0x04a0
#define SEC_CSR17			0x04a2
#define SEC_CSR18			0X04A4
#define SEC_CSR19			0x04a6
#define SEC_CSR20			0x04a8