📄 rt2500pci.h

📁 linux内核源码
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#define MACCSR2_DELAY			FIELD32(0x000000ff)/* * TESTCSR: TEST mode selection register. */#define TESTCSR				0x0138/* * ARCSR2: 1 Mbps ACK/CTS PLCP. */#define ARCSR2				0x013c#define ARCSR2_SIGNAL			FIELD32(0x000000ff)#define ARCSR2_SERVICE			FIELD32(0x0000ff00)#define ARCSR2_LENGTH			FIELD32(0xffff0000)/* * ARCSR3: 2 Mbps ACK/CTS PLCP. */#define ARCSR3				0x0140#define ARCSR3_SIGNAL			FIELD32(0x000000ff)#define ARCSR3_SERVICE			FIELD32(0x0000ff00)#define ARCSR3_LENGTH			FIELD32(0xffff0000)/* * ARCSR4: 5.5 Mbps ACK/CTS PLCP. */#define ARCSR4				0x0144#define ARCSR4_SIGNAL			FIELD32(0x000000ff)#define ARCSR4_SERVICE			FIELD32(0x0000ff00)#define ARCSR4_LENGTH			FIELD32(0xffff0000)/* * ARCSR5: 11 Mbps ACK/CTS PLCP. */#define ARCSR5				0x0148#define ARCSR5_SIGNAL			FIELD32(0x000000ff)#define ARCSR5_SERVICE			FIELD32(0x0000ff00)#define ARCSR5_LENGTH			FIELD32(0xffff0000)/* * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps. */#define ARTCSR0				0x014c#define ARTCSR0_ACK_CTS_11MBS		FIELD32(0x000000ff)#define ARTCSR0_ACK_CTS_5_5MBS		FIELD32(0x0000ff00)#define ARTCSR0_ACK_CTS_2MBS		FIELD32(0x00ff0000)#define ARTCSR0_ACK_CTS_1MBS		FIELD32(0xff000000)/* * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps. */#define ARTCSR1				0x0150#define ARTCSR1_ACK_CTS_6MBS		FIELD32(0x000000ff)#define ARTCSR1_ACK_CTS_9MBS		FIELD32(0x0000ff00)#define ARTCSR1_ACK_CTS_12MBS		FIELD32(0x00ff0000)#define ARTCSR1_ACK_CTS_18MBS		FIELD32(0xff000000)/* * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps. */#define ARTCSR2				0x0154#define ARTCSR2_ACK_CTS_24MBS		FIELD32(0x000000ff)#define ARTCSR2_ACK_CTS_36MBS		FIELD32(0x0000ff00)#define ARTCSR2_ACK_CTS_48MBS		FIELD32(0x00ff0000)#define ARTCSR2_ACK_CTS_54MBS		FIELD32(0xff000000)/* * SECCSR1_RT2509: WEP control register. * KICK_ENCRYPT: Kick encryption engine, self-clear. * ONE_SHOT: 0: ring mode, 1: One shot only mode. * DESC_ADDRESS: Descriptor physical address of frame. */#define SECCSR1				0x0158#define SECCSR1_KICK_ENCRYPT		FIELD32(0x00000001)#define SECCSR1_ONE_SHOT		FIELD32(0x00000002)#define SECCSR1_DESC_ADDRESS		FIELD32(0xfffffffc)/* * BBPCSR1: BBP TX configuration. */#define BBPCSR1				0x015c#define BBPCSR1_CCK			FIELD32(0x00000003)#define BBPCSR1_CCK_FLIP		FIELD32(0x00000004)#define BBPCSR1_OFDM			FIELD32(0x00030000)#define BBPCSR1_OFDM_FLIP		FIELD32(0x00040000)/* * Dual band configuration registers. * DBANDCSR0: Dual band configuration register 0. * DBANDCSR1: Dual band configuration register 1. */#define DBANDCSR0			0x0160#define DBANDCSR1			0x0164/* * BBPPCSR: BBP Pin control register. */#define BBPPCSR				0x0168/* * MAC special debug mode selection registers. * DBGSEL0: MAC special debug mode selection register 0. * DBGSEL1: MAC special debug mode selection register 1. */#define DBGSEL0				0x016c#define DBGSEL1				0x0170/* * BISTCSR: BBP BIST register. */#define BISTCSR				0x0174/* * Multicast filter registers. * MCAST0: Multicast filter register 0. * MCAST1: Multicast filter register 1. */#define MCAST0				0x0178#define MCAST1				0x017c/* * UART registers. * UARTCSR0: UART1 TX register. * UARTCSR1: UART1 RX register. * UARTCSR3: UART1 frame control register. * UARTCSR4: UART1 buffer control register. * UART2CSR0: UART2 TX register. * UART2CSR1: UART2 RX register. * UART2CSR3: UART2 frame control register. * UART2CSR4: UART2 buffer control register. */#define UARTCSR0			0x0180#define UARTCSR1			0x0184#define UARTCSR3			0x0188#define UARTCSR4			0x018c#define UART2CSR0			0x0190#define UART2CSR1			0x0194#define UART2CSR3			0x0198#define UART2CSR4			0x019c/* * BBP registers. * The wordsize of the BBP is 8 bits. *//* * R2: TX antenna control */#define BBP_R2_TX_ANTENNA		FIELD8(0x03)#define BBP_R2_TX_IQ_FLIP		FIELD8(0x04)/* * R14: RX antenna control */#define BBP_R14_RX_ANTENNA		FIELD8(0x03)#define BBP_R14_RX_IQ_FLIP		FIELD8(0x04)/* * BBP_R70 */#define BBP_R70_JAPAN_FILTER		FIELD8(0x08)/* * RF registers *//* * RF 1 */#define RF1_TUNER			FIELD32(0x00020000)/* * RF 3 */#define RF3_TUNER			FIELD32(0x00000100)#define RF3_TXPOWER			FIELD32(0x00003e00)/* * EEPROM content. * The wordsize of the EEPROM is 16 bits. *//* * HW MAC address. */#define EEPROM_MAC_ADDR_0		0x0002#define EEPROM_MAC_ADDR_BYTE0		FIELD16(0x00ff)#define EEPROM_MAC_ADDR_BYTE1		FIELD16(0xff00)#define EEPROM_MAC_ADDR1		0x0003#define EEPROM_MAC_ADDR_BYTE2		FIELD16(0x00ff)#define EEPROM_MAC_ADDR_BYTE3		FIELD16(0xff00)#define EEPROM_MAC_ADDR_2		0x0004#define EEPROM_MAC_ADDR_BYTE4		FIELD16(0x00ff)#define EEPROM_MAC_ADDR_BYTE5		FIELD16(0xff00)/* * EEPROM antenna. * ANTENNA_NUM: Number of antenna's. * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd. * DYN_TXAGC: Dynamic TX AGC control. * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. * RF_TYPE: Rf_type of this adapter. */#define EEPROM_ANTENNA			0x10#define EEPROM_ANTENNA_NUM		FIELD16(0x0003)#define EEPROM_ANTENNA_TX_DEFAULT	FIELD16(0x000c)#define EEPROM_ANTENNA_RX_DEFAULT	FIELD16(0x0030)#define EEPROM_ANTENNA_LED_MODE		FIELD16(0x01c0)#define EEPROM_ANTENNA_DYN_TXAGC	FIELD16(0x0200)#define EEPROM_ANTENNA_HARDWARE_RADIO	FIELD16(0x0400)#define EEPROM_ANTENNA_RF_TYPE		FIELD16(0xf800)/* * EEPROM NIC config. * CARDBUS_ACCEL: 0: enable, 1: disable. * DYN_BBP_TUNE: 0: enable, 1: disable. * CCK_TX_POWER: CCK TX power compensation. */#define EEPROM_NIC			0x11#define EEPROM_NIC_CARDBUS_ACCEL	FIELD16(0x0001)#define EEPROM_NIC_DYN_BBP_TUNE		FIELD16(0x0002)#define EEPROM_NIC_CCK_TX_POWER		FIELD16(0x000c)/* * EEPROM geography. * GEO: Default geography setting for device. */#define EEPROM_GEOGRAPHY		0x12#define EEPROM_GEOGRAPHY_GEO		FIELD16(0x0f00)/* * EEPROM BBP. */#define EEPROM_BBP_START		0x13#define EEPROM_BBP_SIZE			16#define EEPROM_BBP_VALUE		FIELD16(0x00ff)#define EEPROM_BBP_REG_ID		FIELD16(0xff00)/* * EEPROM TXPOWER */#define EEPROM_TXPOWER_START		0x23#define EEPROM_TXPOWER_SIZE		7#define EEPROM_TXPOWER_1		FIELD16(0x00ff)#define EEPROM_TXPOWER_2		FIELD16(0xff00)/* * RSSI <-> dBm offset calibration */#define EEPROM_CALIBRATE_OFFSET		0x3e#define EEPROM_CALIBRATE_OFFSET_RSSI	FIELD16(0x00ff)/* * DMA descriptor defines. */#define TXD_DESC_SIZE			( 11 * sizeof(struct data_desc) )#define RXD_DESC_SIZE			( 11 * sizeof(struct data_desc) )/* * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. *//* * Word0 */#define TXD_W0_OWNER_NIC		FIELD32(0x00000001)#define TXD_W0_VALID			FIELD32(0x00000002)#define TXD_W0_RESULT			FIELD32(0x0000001c)#define TXD_W0_RETRY_COUNT		FIELD32(0x000000e0)#define TXD_W0_MORE_FRAG		FIELD32(0x00000100)#define TXD_W0_ACK			FIELD32(0x00000200)#define TXD_W0_TIMESTAMP		FIELD32(0x00000400)#define TXD_W0_OFDM			FIELD32(0x00000800)#define TXD_W0_CIPHER_OWNER		FIELD32(0x00001000)#define TXD_W0_IFS			FIELD32(0x00006000)#define TXD_W0_RETRY_MODE		FIELD32(0x00008000)#define TXD_W0_DATABYTE_COUNT		FIELD32(0x0fff0000)#define TXD_W0_CIPHER_ALG		FIELD32(0xe0000000)/* * Word1 */#define TXD_W1_BUFFER_ADDRESS		FIELD32(0xffffffff)/* * Word2 */#define TXD_W2_IV_OFFSET		FIELD32(0x0000003f)#define TXD_W2_AIFS			FIELD32(0x000000c0)#define TXD_W2_CWMIN			FIELD32(0x00000f00)#define TXD_W2_CWMAX			FIELD32(0x0000f000)/* * Word3: PLCP information */#define TXD_W3_PLCP_SIGNAL		FIELD32(0x000000ff)#define TXD_W3_PLCP_SERVICE		FIELD32(0x0000ff00)#define TXD_W3_PLCP_LENGTH_LOW		FIELD32(0x00ff0000)#define TXD_W3_PLCP_LENGTH_HIGH		FIELD32(0xff000000)/* * Word4 */#define TXD_W4_IV			FIELD32(0xffffffff)/* * Word5 */#define TXD_W5_EIV			FIELD32(0xffffffff)/* * Word6-9: Key */#define TXD_W6_KEY			FIELD32(0xffffffff)#define TXD_W7_KEY			FIELD32(0xffffffff)#define TXD_W8_KEY			FIELD32(0xffffffff)#define TXD_W9_KEY			FIELD32(0xffffffff)/* * Word10 */#define TXD_W10_RTS			FIELD32(0x00000001)#define TXD_W10_TX_RATE			FIELD32(0x000000fe)/* * RX descriptor format for RX Ring. *//* * Word0 */#define RXD_W0_OWNER_NIC		FIELD32(0x00000001)#define RXD_W0_UNICAST_TO_ME		FIELD32(0x00000002)#define RXD_W0_MULTICAST		FIELD32(0x00000004)#define RXD_W0_BROADCAST		FIELD32(0x00000008)#define RXD_W0_MY_BSS			FIELD32(0x00000010)#define RXD_W0_CRC_ERROR		FIELD32(0x00000020)#define RXD_W0_OFDM			FIELD32(0x00000040)#define RXD_W0_PHYSICAL_ERROR		FIELD32(0x00000080)#define RXD_W0_CIPHER_OWNER		FIELD32(0x00000100)#define RXD_W0_ICV_ERROR		FIELD32(0x00000200)#define RXD_W0_IV_OFFSET		FIELD32(0x0000fc00)#define RXD_W0_DATABYTE_COUNT		FIELD32(0x0fff0000)#define RXD_W0_CIPHER_ALG		FIELD32(0xe0000000)/* * Word1 */#define RXD_W1_BUFFER_ADDRESS		FIELD32(0xffffffff)/* * Word2 */#define RXD_W2_SIGNAL			FIELD32(0x000000ff)#define RXD_W2_RSSI			FIELD32(0x0000ff00)#define RXD_W2_TA			FIELD32(0xffff0000)/* * Word3 */#define RXD_W3_TA			FIELD32(0xffffffff)/* * Word4 */#define RXD_W4_IV			FIELD32(0xffffffff)/* * Word5 */#define RXD_W5_EIV			FIELD32(0xffffffff)/* * Word6-9: Key */#define RXD_W6_KEY			FIELD32(0xffffffff)#define RXD_W7_KEY			FIELD32(0xffffffff)#define RXD_W8_KEY			FIELD32(0xffffffff)#define RXD_W9_KEY			FIELD32(0xffffffff)/* * Word10 */#define RXD_W10_DROP			FIELD32(0x00000001)/* * Macro's for converting txpower from EEPROM to dscape value * and from dscape value to register value. */#define MIN_TXPOWER	0#define MAX_TXPOWER	31#define DEFAULT_TXPOWER	24#define TXPOWER_FROM_DEV(__txpower)		\({						\	((__txpower) > MAX_TXPOWER) ?		\		DEFAULT_TXPOWER : (__txpower);	\})#define TXPOWER_TO_DEV(__txpower)			\({							\	((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER :	\	(((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER :	\	(__txpower));					\})#endif /* RT2500PCI_H */
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