rt2500pci.h

linux内核源码

#define TXCSR3_TX_RING_REGISTER		FIELD32(0xffffffff)

/*
 * TXCSR4: TX Atim Ring Base address register.
 */
#define TXCSR4				0x0070
#define TXCSR4_ATIM_RING_REGISTER	FIELD32(0xffffffff)

/*
 * TXCSR5: TX Prio Ring Base address register.
 */
#define TXCSR5				0x0074
#define TXCSR5_PRIO_RING_REGISTER	FIELD32(0xffffffff)

/*
 * TXCSR6: Beacon Base address register.
 */
#define TXCSR6				0x0078
#define TXCSR6_BEACON_RING_REGISTER	FIELD32(0xffffffff)

/*
 * TXCSR7: Auto responder control register.
 * AR_POWERMANAGEMENT: Auto responder power management bit.
 */
#define TXCSR7				0x007c
#define TXCSR7_AR_POWERMANAGEMENT	FIELD32(0x00000001)

/*
 * TXCSR8: CCK Tx BBP register.
 */
#define TXCSR8				0x0098
#define TXCSR8_BBP_ID0			FIELD32(0x0000007f)
#define TXCSR8_BBP_ID0_VALID		FIELD32(0x00000080)
#define TXCSR8_BBP_ID1			FIELD32(0x00007f00)
#define TXCSR8_BBP_ID1_VALID		FIELD32(0x00008000)
#define TXCSR8_BBP_ID2			FIELD32(0x007f0000)
#define TXCSR8_BBP_ID2_VALID		FIELD32(0x00800000)
#define TXCSR8_BBP_ID3			FIELD32(0x7f000000)
#define TXCSR8_BBP_ID3_VALID		FIELD32(0x80000000)

/*
 * TXCSR9: OFDM TX BBP registers
 * OFDM_SIGNAL: BBP rate field address for OFDM.
 * OFDM_SERVICE: BBP service field address for OFDM.
 * OFDM_LENGTH_LOW: BBP length low byte address for OFDM.
 * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM.
 */
#define TXCSR9				0x0094
#define TXCSR9_OFDM_RATE		FIELD32(0x000000ff)
#define TXCSR9_OFDM_SERVICE		FIELD32(0x0000ff00)
#define TXCSR9_OFDM_LENGTH_LOW		FIELD32(0x00ff0000)
#define TXCSR9_OFDM_LENGTH_HIGH		FIELD32(0xff000000)

/*
 * Receive related CSRs.
 * Some values are set in TU, whereas 1 TU == 1024 us.
 */

/*
 * RXCSR0: RX Control Register.
 * DISABLE_RX: Disable rx engine.
 * DROP_CRC: Drop crc error.
 * DROP_PHYSICAL: Drop physical error.
 * DROP_CONTROL: Drop control frame.
 * DROP_NOT_TO_ME: Drop not to me unicast frame.
 * DROP_TODS: Drop frame tods bit is true.
 * DROP_VERSION_ERROR: Drop version error frame.
 * PASS_CRC: Pass all packets with crc attached.
 * PASS_CRC: Pass all packets with crc attached.
 * PASS_PLCP: Pass all packets with 4 bytes PLCP attached.
 * DROP_MCAST: Drop multicast frames.
 * DROP_BCAST: Drop broadcast frames.
 * ENABLE_QOS: Accept QOS data frame and parse QOS field.
 */
#define RXCSR0				0x0080
#define RXCSR0_DISABLE_RX		FIELD32(0x00000001)
#define RXCSR0_DROP_CRC			FIELD32(0x00000002)
#define RXCSR0_DROP_PHYSICAL		FIELD32(0x00000004)
#define RXCSR0_DROP_CONTROL		FIELD32(0x00000008)
#define RXCSR0_DROP_NOT_TO_ME		FIELD32(0x00000010)
#define RXCSR0_DROP_TODS		FIELD32(0x00000020)
#define RXCSR0_DROP_VERSION_ERROR	FIELD32(0x00000040)
#define RXCSR0_PASS_CRC			FIELD32(0x00000080)
#define RXCSR0_PASS_PLCP		FIELD32(0x00000100)
#define RXCSR0_DROP_MCAST		FIELD32(0x00000200)
#define RXCSR0_DROP_BCAST		FIELD32(0x00000400)
#define RXCSR0_ENABLE_QOS		FIELD32(0x00000800)

/*
 * RXCSR1: RX descriptor configuration register.
 * RXD_SIZE: Rx descriptor size, default is 32b.
 * NUM_RXD: Number of rx entries in ring.
 */
#define RXCSR1				0x0084
#define RXCSR1_RXD_SIZE			FIELD32(0x000000ff)
#define RXCSR1_NUM_RXD			FIELD32(0x0000ff00)

/*
 * RXCSR2: RX Ring base address register.
 */
#define RXCSR2				0x0088
#define RXCSR2_RX_RING_REGISTER		FIELD32(0xffffffff)

/*
 * RXCSR3: BBP ID register for Rx operation.
 * BBP_ID#: BBP register # id.
 * BBP_ID#_VALID: BBP register # id is valid or not.
 */
#define RXCSR3				0x0090
#define RXCSR3_BBP_ID0			FIELD32(0x0000007f)
#define RXCSR3_BBP_ID0_VALID		FIELD32(0x00000080)
#define RXCSR3_BBP_ID1			FIELD32(0x00007f00)
#define RXCSR3_BBP_ID1_VALID		FIELD32(0x00008000)
#define RXCSR3_BBP_ID2			FIELD32(0x007f0000)
#define RXCSR3_BBP_ID2_VALID		FIELD32(0x00800000)
#define RXCSR3_BBP_ID3			FIELD32(0x7f000000)
#define RXCSR3_BBP_ID3_VALID		FIELD32(0x80000000)

/*
 * ARCSR1: Auto Responder PLCP config register 1.
 * AR_BBP_DATA#: Auto responder BBP register # data.
 * AR_BBP_ID#: Auto responder BBP register # Id.
 */
#define ARCSR1				0x009c
#define ARCSR1_AR_BBP_DATA2		FIELD32(0x000000ff)
#define ARCSR1_AR_BBP_ID2		FIELD32(0x0000ff00)
#define ARCSR1_AR_BBP_DATA3		FIELD32(0x00ff0000)
#define ARCSR1_AR_BBP_ID3		FIELD32(0xff000000)

/*
 * Miscellaneous Registers.
 * Some values are set in TU, whereas 1 TU == 1024 us.

 */

/*
 * PCICSR: PCI control register.
 * BIG_ENDIAN: 1: big endian, 0: little endian.
 * RX_TRESHOLD: Rx threshold in dw to start pci access
 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
 * TX_TRESHOLD: Tx threshold in dw to start pci access
 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
 * READ_MULTIPLE: Enable memory read multiple.
 * WRITE_INVALID: Enable memory write & invalid.
 */
#define PCICSR				0x008c
#define PCICSR_BIG_ENDIAN		FIELD32(0x00000001)
#define PCICSR_RX_TRESHOLD		FIELD32(0x00000006)
#define PCICSR_TX_TRESHOLD		FIELD32(0x00000018)
#define PCICSR_BURST_LENTH		FIELD32(0x00000060)
#define PCICSR_ENABLE_CLK		FIELD32(0x00000080)
#define PCICSR_READ_MULTIPLE		FIELD32(0x00000100)
#define PCICSR_WRITE_INVALID		FIELD32(0x00000200)

/*
 * CNT0: FCS error count.
 * FCS_ERROR: FCS error count, cleared when read.
 */
#define CNT0				0x00a0
#define CNT0_FCS_ERROR			FIELD32(0x0000ffff)

/*
 * Statistic Register.
 * CNT1: PLCP error count.
 * CNT2: Long error count.
 */
#define TIMECSR2			0x00a8
#define CNT1				0x00ac
#define CNT2				0x00b0
#define TIMECSR3			0x00b4

/*
 * CNT3: CCA false alarm count.
 */
#define CNT3				0x00b8
#define CNT3_FALSE_CCA			FIELD32(0x0000ffff)

/*
 * Statistic Register.
 * CNT4: Rx FIFO overflow count.
 * CNT5: Tx FIFO underrun count.
 */
#define CNT4				0x00bc
#define CNT5				0x00c0

/*
 * Baseband Control Register.
 */

/*
 * PWRCSR0: Power mode configuration register.
 */
#define PWRCSR0				0x00c4

/*
 * Power state transition time registers.
 */
#define PSCSR0				0x00c8
#define PSCSR1				0x00cc
#define PSCSR2				0x00d0
#define PSCSR3				0x00d4

/*
 * PWRCSR1: Manual power control / status register.
 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
 * SET_STATE: Set state. Write 1 to trigger, self cleared.
 * BBP_DESIRE_STATE: BBP desired state.
 * RF_DESIRE_STATE: RF desired state.
 * BBP_CURR_STATE: BBP current state.
 * RF_CURR_STATE: RF current state.
 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
 */
#define PWRCSR1				0x00d8
#define PWRCSR1_SET_STATE		FIELD32(0x00000001)
#define PWRCSR1_BBP_DESIRE_STATE	FIELD32(0x00000006)
#define PWRCSR1_RF_DESIRE_STATE		FIELD32(0x00000018)
#define PWRCSR1_BBP_CURR_STATE		FIELD32(0x00000060)
#define PWRCSR1_RF_CURR_STATE		FIELD32(0x00000180)
#define PWRCSR1_PUT_TO_SLEEP		FIELD32(0x00000200)

/*
 * TIMECSR: Timer control register.
 * US_COUNT: 1 us timer count in units of clock cycles.
 * US_64_COUNT: 64 us timer count in units of 1 us timer.
 * BEACON_EXPECT: Beacon expect window.
 */
#define TIMECSR				0x00dc
#define TIMECSR_US_COUNT		FIELD32(0x000000ff)
#define TIMECSR_US_64_COUNT		FIELD32(0x0000ff00)
#define TIMECSR_BEACON_EXPECT		FIELD32(0x00070000)

/*
 * MACCSR0: MAC configuration register 0.
 */
#define MACCSR0				0x00e0

/*
 * MACCSR1: MAC configuration register 1.
 * KICK_RX: Kick one-shot rx in one-shot rx mode.
 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
 * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
 * AUTO_TXBBP: Auto tx logic access bbp control register.
 * AUTO_RXBBP: Auto rx logic access bbp control register.
 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
 * INTERSIL_IF: Intersil if calibration pin.
 */
#define MACCSR1				0x00e4
#define MACCSR1_KICK_RX			FIELD32(0x00000001)
#define MACCSR1_ONESHOT_RXMODE		FIELD32(0x00000002)
#define MACCSR1_BBPRX_RESET_MODE	FIELD32(0x00000004)
#define MACCSR1_AUTO_TXBBP		FIELD32(0x00000008)
#define MACCSR1_AUTO_RXBBP		FIELD32(0x00000010)
#define MACCSR1_LOOPBACK		FIELD32(0x00000060)
#define MACCSR1_INTERSIL_IF		FIELD32(0x00000080)

/*
 * RALINKCSR: Ralink Rx auto-reset BBCR.
 * AR_BBP_DATA#: Auto reset BBP register # data.
 * AR_BBP_ID#: Auto reset BBP register # id.
 */
#define RALINKCSR			0x00e8
#define RALINKCSR_AR_BBP_DATA0		FIELD32(0x000000ff)
#define RALINKCSR_AR_BBP_ID0		FIELD32(0x00007f00)
#define RALINKCSR_AR_BBP_VALID0		FIELD32(0x00008000)
#define RALINKCSR_AR_BBP_DATA1		FIELD32(0x00ff0000)
#define RALINKCSR_AR_BBP_ID1		FIELD32(0x7f000000)
#define RALINKCSR_AR_BBP_VALID1		FIELD32(0x80000000)

/*
 * BCNCSR: Beacon interval control register.
 * CHANGE: Write one to change beacon interval.
 * DELTATIME: The delta time value.
 * NUM_BEACON: Number of beacon according to mode.
 * MODE: Please refer to asic specs.
 * PLUS: Plus or minus delta time value.
 */
#define BCNCSR				0x00ec
#define BCNCSR_CHANGE			FIELD32(0x00000001)
#define BCNCSR_DELTATIME		FIELD32(0x0000001e)
#define BCNCSR_NUM_BEACON		FIELD32(0x00001fe0)
#define BCNCSR_MODE			FIELD32(0x00006000)
#define BCNCSR_PLUS			FIELD32(0x00008000)

/*
 * BBP / RF / IF Control Register.
 */

/*
 * BBPCSR: BBP serial control register.
 * VALUE: Register value to program into BBP.
 * REGNUM: Selected BBP register.
 * BUSY: 1: asic is busy execute BBP programming.
 * WRITE_CONTROL: 1: write BBP, 0: read BBP.
 */
#define BBPCSR				0x00f0
#define BBPCSR_VALUE			FIELD32(0x000000ff)
#define BBPCSR_REGNUM			FIELD32(0x00007f00)
#define BBPCSR_BUSY			FIELD32(0x00008000)
#define BBPCSR_WRITE_CONTROL		FIELD32(0x00010000)

/*
 * RFCSR: RF serial control register.
 * VALUE: Register value + id to program into rf/if.
 * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
 * IF_SELECT: Chip to program: 0: rf, 1: if.
 * PLL_LD: Rf pll_ld status.
 * BUSY: 1: asic is busy execute rf programming.
 */
#define RFCSR				0x00f4
#define RFCSR_VALUE			FIELD32(0x00ffffff)
#define RFCSR_NUMBER_OF_BITS		FIELD32(0x1f000000)
#define RFCSR_IF_SELECT			FIELD32(0x20000000)
#define RFCSR_PLL_LD			FIELD32(0x40000000)
#define RFCSR_BUSY			FIELD32(0x80000000)

/*
 * LEDCSR: LED control register.
 * ON_PERIOD: On period, default 70ms.
 * OFF_PERIOD: Off period, default 30ms.
 * LINK: 0: linkoff, 1: linkup.
 * ACTIVITY: 0: idle, 1: active.
 * LINK_POLARITY: 0: active low, 1: active high.
 * ACTIVITY_POLARITY: 0: active low, 1: active high.
 * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF.
 */
#define LEDCSR				0x00f8
#define LEDCSR_ON_PERIOD		FIELD32(0x000000ff)
#define LEDCSR_OFF_PERIOD		FIELD32(0x0000ff00)
#define LEDCSR_LINK			FIELD32(0x00010000)
#define LEDCSR_ACTIVITY			FIELD32(0x00020000)
#define LEDCSR_LINK_POLARITY		FIELD32(0x00040000)
#define LEDCSR_ACTIVITY_POLARITY	FIELD32(0x00080000)
#define LEDCSR_LED_DEFAULT		FIELD32(0x00100000)

/*
 * AES control register.
 */
#define SECCSR3				0x00fc

/*
 * ASIC pointer information.
 * RXPTR: Current RX ring address.
 * TXPTR: Current Tx ring address.
 * PRIPTR: Current Priority ring address.
 * ATIMPTR: Current ATIM ring address.
 */
#define RXPTR				0x0100
#define TXPTR				0x0104
#define PRIPTR				0x0108
#define ATIMPTR				0x010c

/*
 * TXACKCSR0: TX ACK timeout.
 */
#define TXACKCSR0			0x0110

/*
 * ACK timeout count registers.
 * ACKCNT0: TX ACK timeout count.
 * ACKCNT1: RX ACK timeout count.
 */
#define ACKCNT0				0x0114
#define ACKCNT1				0x0118

/*
 * GPIO and others.
 */

/*
 * GPIOCSR: GPIO control register.
 */
#define GPIOCSR				0x0120
#define GPIOCSR_BIT0			FIELD32(0x00000001)
#define GPIOCSR_BIT1			FIELD32(0x00000002)
#define GPIOCSR_BIT2			FIELD32(0x00000004)
#define GPIOCSR_BIT3			FIELD32(0x00000008)
#define GPIOCSR_BIT4			FIELD32(0x00000010)
#define GPIOCSR_BIT5			FIELD32(0x00000020)
#define GPIOCSR_BIT6			FIELD32(0x00000040)
#define GPIOCSR_BIT7			FIELD32(0x00000080)
#define GPIOCSR_DIR0			FIELD32(0x00000100)
#define GPIOCSR_DIR1			FIELD32(0x00000200)
#define GPIOCSR_DIR2			FIELD32(0x00000400)
#define GPIOCSR_DIR3			FIELD32(0x00000800)
#define GPIOCSR_DIR4			FIELD32(0x00001000)
#define GPIOCSR_DIR5			FIELD32(0x00002000)
#define GPIOCSR_DIR6			FIELD32(0x00004000)
#define GPIOCSR_DIR7			FIELD32(0x00008000)

/*
 * FIFO pointer registers.
 * FIFOCSR0: TX FIFO pointer.
 * FIFOCSR1: RX FIFO pointer.
 */
#define FIFOCSR0			0x0128
#define FIFOCSR1			0x012c

/*
 * BCNCSR1: Tx BEACON offset time control register.
 * PRELOAD: Beacon timer offset in units of usec.
 * BEACON_CWMIN: 2^CwMin.
 */
#define BCNCSR1				0x0130
#define BCNCSR1_PRELOAD			FIELD32(0x0000ffff)
#define BCNCSR1_BEACON_CWMIN		FIELD32(0x000f0000)

/*
 * MACCSR2: TX_PE to RX_PE turn-around time control register
 * DELAY: RX_PE low width, in units of pci clock cycle.
 */
#define MACCSR2				0x0134