📄 mpi_cnfg.h
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{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 Reserved1; /* 04h */ U32 Reserved2; /* 08h */ U32 Flags; /* 0Ch */ U8 EnclosureName[16]; /* 10h */ U8 NumPhys; /* 20h */ U8 Reserved3; /* 21h */ U16 Reserved4; /* 22h */ MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */} CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7, ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t;#define MPI_MANUFACTURING7_PAGEVERSION (0x00)/* defines for the Flags field */#define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)typedef struct _CONFIG_PAGE_MANUFACTURING_8{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 ProductSpecificInfo;/* 04h */} CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8, ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t;#define MPI_MANUFACTURING8_PAGEVERSION (0x00)typedef struct _CONFIG_PAGE_MANUFACTURING_9{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 ProductSpecificInfo;/* 04h */} CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9, ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t;#define MPI_MANUFACTURING9_PAGEVERSION (0x00)typedef struct _CONFIG_PAGE_MANUFACTURING_10{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 ProductSpecificInfo;/* 04h */} CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10, ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t;#define MPI_MANUFACTURING10_PAGEVERSION (0x00)/***************************************************************************** IO Unit Config Pages****************************************************************************/typedef struct _CONFIG_PAGE_IO_UNIT_0{ CONFIG_PAGE_HEADER Header; /* 00h */ U64 UniqueValue; /* 04h */} CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;#define MPI_IOUNITPAGE0_PAGEVERSION (0x00)typedef struct _CONFIG_PAGE_IO_UNIT_1{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 Flags; /* 04h */} CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;#define MPI_IOUNITPAGE1_PAGEVERSION (0x02)/* IO Unit Page 1 Flags defines */#define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)#define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)#define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)#define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)#define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)#define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)#define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)#define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)#define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)#define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200)typedef struct _MPI_ADAPTER_INFO{ U8 PciBusNumber; /* 00h */ U8 PciDeviceAndFunctionNumber; /* 01h */ U16 AdapterFlags; /* 02h */} MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;#define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)#define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)typedef struct _CONFIG_PAGE_IO_UNIT_2{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 Flags; /* 04h */ U32 BiosVersion; /* 08h */ MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ U32 Reserved1; /* 1Ch */} CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;#define MPI_IOUNITPAGE2_PAGEVERSION (0x02)#define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)#define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)#define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)#define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)#define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)#define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)#define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)/* * Host code (drivers, BIOS, utilities, etc.) should leave this define set to * one and check Header.PageLength at runtime. */#ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX#define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)#endiftypedef struct _CONFIG_PAGE_IO_UNIT_3{ CONFIG_PAGE_HEADER Header; /* 00h */ U8 GPIOCount; /* 04h */ U8 Reserved1; /* 05h */ U16 Reserved2; /* 06h */ U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */} CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;#define MPI_IOUNITPAGE3_PAGEVERSION (0x01)#define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)#define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)#define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)#define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)typedef struct _CONFIG_PAGE_IO_UNIT_4{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 Reserved1; /* 04h */ SGE_SIMPLE_UNION FWImageSGE; /* 08h */} CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4, IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;#define MPI_IOUNITPAGE4_PAGEVERSION (0x00)/***************************************************************************** IOC Config Pages****************************************************************************/typedef struct _CONFIG_PAGE_IOC_0{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 TotalNVStore; /* 04h */ U32 FreeNVStore; /* 08h */ U16 VendorID; /* 0Ch */ U16 DeviceID; /* 0Eh */ U8 RevisionID; /* 10h */ U8 Reserved[3]; /* 11h */ U32 ClassCode; /* 14h */ U16 SubsystemVendorID; /* 18h */ U16 SubsystemID; /* 1Ah */} CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, IOCPage0_t, MPI_POINTER pIOCPage0_t;#define MPI_IOCPAGE0_PAGEVERSION (0x01)typedef struct _CONFIG_PAGE_IOC_1{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 Flags; /* 04h */ U32 CoalescingTimeout; /* 08h */ U8 CoalescingDepth; /* 0Ch */ U8 PCISlotNum; /* 0Dh */ U8 Reserved[2]; /* 0Eh */} CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, IOCPage1_t, MPI_POINTER pIOCPage1_t;#define MPI_IOCPAGE1_PAGEVERSION (0x03)/* defines for the Flags field */#define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000)#define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000)#define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000)#define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000)#define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010)#define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)#define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL{ U8 VolumeID; /* 00h */ U8 VolumeBus; /* 01h */ U8 VolumeIOC; /* 02h */ U8 VolumePageNumber; /* 03h */ U8 VolumeType; /* 04h */ U8 Flags; /* 05h */ U16 Reserved3; /* 06h */} CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;/* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */#define MPI_RAID_VOL_TYPE_IS (0x00)#define MPI_RAID_VOL_TYPE_IME (0x01)#define MPI_RAID_VOL_TYPE_IM (0x02)#define MPI_RAID_VOL_TYPE_RAID_5 (0x03)#define MPI_RAID_VOL_TYPE_RAID_6 (0x04)#define MPI_RAID_VOL_TYPE_RAID_10 (0x05)#define MPI_RAID_VOL_TYPE_RAID_50 (0x06)#define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF)/* IOC Page 2 Volume Flags values */#define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)/* * Host code (drivers, BIOS, utilities, etc.) should leave this define set to * one and check Header.PageLength at runtime. */#ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX#define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)#endiftypedef struct _CONFIG_PAGE_IOC_2{ CONFIG_PAGE_HEADER Header; /* 00h */ U32 CapabilitiesFlags; /* 04h */ U8 NumActiveVolumes; /* 08h */ U8 MaxVolumes; /* 09h */ U8 NumActivePhysDisks; /* 0Ah */ U8 MaxPhysDisks; /* 0Bh */ CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */} CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, IOCPage2_t, MPI_POINTER pIOCPage2_t;#define MPI_IOCPAGE2_PAGEVERSION (0x04)/* IOC Page 2 Capabilities flags */#define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)#define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)#define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)#define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008)⌨️ 快捷键说明
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