ppc_40x.h

linux内核源码

| OPB bridge.
+----------------------------------------------------------------------------*/
#define opbw0_gesr      0x0b0               /* error status reg              */
#define opbw0_gesrs     0x0b1               /* error status reg              */
#define opbw0_gear      0x0b2               /* error address reg             */

/*----------------------------------------------------------------------------+
| DMA.
+----------------------------------------------------------------------------*/
#define dma0_cr0        0x0c0               /* DMA channel control reg 0     */
#define dma0_ct0        0x0c1               /* DMA count register 0          */
#define dma0_da0        0x0c2               /* DMA destination addr reg 0    */
#define dma0_sa0        0x0c3               /* DMA source addr register 0    */
#define dma0_cc0        0x0c4               /* DMA chained count 0           */
#define dma0_cr1        0x0c8               /* DMA channel control reg 1     */
#define dma0_ct1        0x0c9               /* DMA count register 1          */
#define dma0_da1        0x0ca               /* DMA destination addr reg 1    */
#define dma0_sa1        0x0cb               /* DMA source addr register 1    */
#define dma0_cc1        0x0cc               /* DMA chained count 1           */
#define dma0_cr2        0x0d0               /* DMA channel control reg 2     */
#define dma0_ct2        0x0d1               /* DMA count register 2          */
#define dma0_da2        0x0d2               /* DMA destination addr reg 2    */
#define dma0_sa2        0x0d3               /* DMA source addr register 2    */
#define dma0_cc2        0x0d4               /* DMA chained count 2           */
#define dma0_cr3        0x0d8               /* DMA channel control reg 3     */
#define dma0_ct3        0x0d9               /* DMA count register 3          */
#define dma0_da3        0x0da               /* DMA destination addr reg 3    */
#define dma0_sa3        0x0db               /* DMA source addr register 3    */
#define dma0_cc3        0x0dc               /* DMA chained count 3           */
#define dma0_sr         0x0e0               /* DMA status register           */
#define dma0_srs        0x0e1               /* DMA status register           */
#define dma0_s1         0x031               /* DMA select1 register          */
#define dma0_s2         0x032               /* DMA select2 register          */

/*---------------------------------------------------------------------------+
| Clock and power management.
+----------------------------------------------------------------------------*/
#define cpm0_fr         0x102               /* force register                */

/*----------------------------------------------------------------------------+
| Serial Clock Control.
+----------------------------------------------------------------------------*/
#define ser0_ccr        0x120               /* serial clock control register */

/*----------------------------------------------------------------------------+
| Audio Clock Control.
+----------------------------------------------------------------------------*/
#define aud0_apcr       0x121               /* audio clock ctrl register     */

/*----------------------------------------------------------------------------+
| DENC.
+----------------------------------------------------------------------------*/
#define denc0_idr       0x130               /* DENC ID register              */
#define denc0_cr1       0x131               /* control register 1            */
#define denc0_rr1       0x132               /* microvision 1 (reserved 1)    */
#define denc0_cr2       0x133               /* control register 2            */
#define denc0_rr2       0x134               /* microvision 2 (reserved 2)    */
#define denc0_rr3       0x135               /* microvision 3 (reserved 3)    */
#define denc0_rr4       0x136               /* microvision 4 (reserved 4)    */
#define denc0_rr5       0x137               /* microvision 5 (reserved 5)    */
#define denc0_ccdr      0x138               /* closed caption data           */
#define denc0_cccr      0x139               /* closed caption control        */
#define denc0_trr       0x13A               /* teletext request register     */
#define denc0_tosr      0x13B               /* teletext odd field line se    */
#define denc0_tesr      0x13C               /* teletext even field line s    */
#define denc0_rlsr      0x13D               /* RGB rhift left register       */
#define denc0_vlsr      0x13E               /* video level shift register    */
#define denc0_vsr       0x13F               /* video scaling register        */

/*----------------------------------------------------------------------------+
| Video decoder.  Suspect 0x179, 0x169, 0x16a, 0x152 (rc).
+----------------------------------------------------------------------------*/
#define vid0_ccntl      0x140               /* control decoder operation     */
#define vid0_cmode      0x141               /* video operational mode        */
#define vid0_sstc0      0x142               /* STC high order bits 31:0      */
#define vid0_sstc1      0x143               /* STC low order bit 32          */
#define vid0_spts0      0x144               /* PTS high order bits 31:0      */
#define vid0_spts1      0x145               /* PTS low order bit 32          */
#define vid0_fifo       0x146               /* FIFO data port                */
#define vid0_fifos      0x147               /* FIFO status                   */
#define vid0_cmd        0x148               /* send command to decoder       */
#define vid0_cmdd       0x149               /* port for command params       */
#define vid0_cmdst      0x14A               /* command status                */
#define vid0_cmdad      0x14B               /* command address               */
#define vid0_procia     0x14C               /* instruction store             */
#define vid0_procid     0x14D               /* data port for I_Store         */
#define vid0_osdm       0x151               /* OSD mode control              */
#define vid0_hosti      0x152               /* base interrupt register       */
#define vid0_mask       0x153               /* interrupt mask register       */
#define vid0_dispm      0x154               /* operational mode for Disp     */
#define vid0_dispd      0x155               /* setting for 'Sync' delay      */
#define vid0_vbctl      0x156               /* VBI                           */
#define vid0_ttxctl     0x157               /* teletext control              */
#define vid0_disptb     0x158               /* display left/top border       */
#define vid0_osdgla     0x159               /* Graphics plane link addr      */
#define vid0_osdila     0x15A               /* Image plane link addr         */
#define vid0_rbthr      0x15B               /* rate buffer threshold         */
#define vid0_osdcla     0x15C               /* Cursor link addr              */
#define vid0_stcca      0x15D               /* STC common address            */
#define vid0_ptsctl     0x15F               /* PTS Control                   */
#define vid0_wprot      0x165               /* write protect for I_Store     */
#define vid0_vcqa       0x167               /* video clip queued block Ad    */
#define vid0_vcql       0x168               /* video clip queued block Le    */
#define vid0_blksz      0x169               /* block size bytes for copy op  */
#define vid0_srcad      0x16a               /* copy source address bits 6-31 */
#define vid0_udbas      0x16B               /* base mem add for user data    */
#define vid0_vbibas     0x16C               /* base mem add for VBI 0/1      */
#define vid0_osdibas    0x16D               /* Image plane base address      */
#define vid0_osdgbas    0x16E               /* Graphic plane base address    */
#define vid0_rbbase     0x16F               /* base mem add for video buf    */
#define vid0_dramad     0x170               /* DRAM address                  */
#define vid0_dramdt     0x171               /* data port for DRAM access     */
#define vid0_dramcs     0x172               /* DRAM command and statusa      */
#define vid0_vcwa       0x173               /* v clip work address           */
#define vid0_vcwl       0x174               /* v clip work length            */
#define vid0_mseg0      0x175               /* segment address 0             */
#define vid0_mseg1      0x176               /* segment address 1             */
#define vid0_mseg2      0x177               /* segment address 2             */
#define vid0_mseg3      0x178               /* segment address 3             */
#define vid0_fbbase     0x179               /* frame buffer base memory      */
#define vid0_osdcbas    0x17A               /* Cursor base addr              */
#define vid0_lboxtb     0x17B               /* top left border               */
#define vid0_trdly      0x17C               /* transparency gate delay       */
#define vid0_sbord      0x17D               /* left/top small pict. bord.    */
#define vid0_zoffs      0x17E               /* hor/ver zoom window           */
#define vid0_rbsz       0x17F               /* rate buffer size read         */

/*----------------------------------------------------------------------------+
| Transport demultiplexer.
+----------------------------------------------------------------------------*/
#define xpt0_lr         0x180               /* demux location register       */
#define xpt0_data       0x181               /* demux data register           */
#define xpt0_ir         0x182               /* demux interrupt register      */

#define xpt0_config1    0x0000              /* configuration 1               */
#define xpt0_control1   0x0001              /* control 1                     */
#define xpt0_festat     0x0002              /* Front-end status              */
#define xpt0_feimask    0x0003              /* Front_end interrupt Mask      */
#define xpt0_ocmcnfg    0x0004              /* OCM Address                   */
#define xpt0_settapi    0x0005              /* Set TAP Interrupt             */

#define xpt0_pcrhi      0x0010              /* PCR High                      */
#define xpt0_pcrlow     0x0011              /* PCR Low                       */
#define xpt0_lstchi     0x0012              /* Latched STC High              */
#define xpt0_lstclow    0x0013              /* Latched STC Low               */
#define xpt0_stchi      0x0014              /* STC High                      */
#define xpt0_stclow     0x0015              /* STC Low                       */
#define xpt0_pwm        0x0016              /* PWM                           */
#define xpt0_pcrstct    0x0017              /* PCR-STC Threshold             */
#define xpt0_pcrstcd    0x0018              /* PCR-STC Delta                 */
#define xpt0_stccomp    0x0019              /* STC Compare                   */
#define xpt0_stccmpd    0x001a              /* STC Compare Disarm            */

#define xpt0_dsstat     0x0048              /* Descrambler Status            */
#define xpt0_dsimask    0x0049              /* Descrambler Interrupt Mask    */

#define xpt0_vcchng     0x01f0              /* Video Channel Change          */
#define xpt0_acchng     0x01f1              /* Audio Channel Change          */
#define xpt0_axenable   0x01fe              /* Aux PID Enables               */
#define xpt0_pcrpid     0x01ff              /* PCR PID                       */

#define xpt0_config2    0x1000              /* Configuration 2               */
#define xpt0_pbuflvl    0x1002              /* Packet Buffer Level           */
#define xpt0_intmask    0x1003              /* Interrupt Mask                */
#define xpt0_plbcnfg    0x1004              /* PLB Configuration             */

#define xpt0_qint       0x1010              /* Queues Interrupts             */
#define xpt0_qintmsk    0x1011              /* Queues Interrupts Mask        */
#define xpt0_astatus    0x1012              /* Audio Status                  */
#define xpt0_aintmask   0x1013              /* Audio Interrupt Mask          */
#define xpt0_vstatus    0x1014              /* Video Status                  */
#define xpt0_vintmask   0x1015              /* Video Interrupt Mask          */

#define xpt0_qbase      0x1020              /* Queue Base                    */
#define xpt0_bucketq    0x1021              /* Bucket Queue                  */
#define xpt0_qstops     0x1024              /* Queue Stops                   */
#define xpt0_qresets    0x1025              /* Queue Resets                  */
#define xpt0_sfchng     0x1026              /* Section Filter Change         */

/*----------------------------------------------------------------------------+
| Audio decoder. Suspect 0x1ad, 0x1b4, 0x1a3, 0x1a5 (read/write status)
+----------------------------------------------------------------------------*/
#define aud0_ctrl0      0x1a0               /* control 0                     */
#define aud0_ctrl1      0x1a1               /* control 1                     */
#define aud0_ctrl2      0x1a2               /* control 2                     */
#define aud0_cmd        0x1a3               /* command register              */
#define aud0_isr        0x1a4               /* interrupt status register     */
#define aud0_imr        0x1a5               /* interrupt mask register       */
#define aud0_dsr        0x1a6               /* decoder status register       */
#define aud0_stc        0x1a7               /* system time clock             */
#define aud0_csr        0x1a8               /* channel status register       */
#define aud0_lcnt       0x1a9               /* queued address register 2     */
#define aud0_pts        0x1aa               /* presentation time stamp       */
#define aud0_tgctrl     0x1ab               /* tone generation control       */
#define aud0_qlr2       0x1ac               /* queued length register 2      */
#define aud0_auxd       0x1ad               /* aux data                      */
#define aud0_strmid     0x1ae               /* stream ID                     */
#define aud0_qar        0x1af               /* queued address register       */
#define aud0_dsps       0x1b0               /* DSP status                    */
#define aud0_qlr        0x1b1               /* queued len address            */
#define aud0_dspc       0x1b2               /* DSP control                   */
#define aud0_wlr2       0x1b3               /* working length register 2     */
#define aud0_instd      0x1b4               /* instruction download          */
#define aud0_war        0x1b5               /* working address register      */
#define aud0_seg1       0x1b6               /* segment 1 base register       */
#define aud0_seg2       0x1b7               /* segment 2 base register       */
#define aud0_avf        0x1b9               /* audio att value front         */
#define aud0_avr        0x1ba               /* audio att value rear          */
#define aud0_avc        0x1bb               /* audio att value center        */
#define aud0_seg3       0x1bc               /* segment 3 base register       */
#define aud0_offset     0x1bd               /* offset address                */
#define aud0_wrl        0x1be               /* working length register       */
#define aud0_war2       0x1bf               /* working address register 2    */

/*----------------------------------------------------------------------------+
| High speed memory controller 0 and 1.
+----------------------------------------------------------------------------*/
#define hsmc0_gr        0x1e0               /* HSMC global register          */
#define hsmc0_besr      0x1e1               /* bus error status register     */
#define hsmc0_bear      0x1e2               /* bus error address register    */
#define hsmc0_br0       0x1e4               /* SDRAM sub-ctrl bank reg 0     */
#define hsmc0_cr0       0x1e5               /* SDRAM sub-ctrl ctrl reg 0     */