rw4_init_brd.s

linux内核源码

        +--------------------------------------------------------------------*/
        li      r10,0                            /* r10 <- 0                 */
        mtdccr  r10                              /* disable the D-Cache      */
        isync                                    /* ensure prev insts done   */

ic_dcinv:
        li      r10,0                            /* r10 <- line address      */
        li      r11,DCACHE_NLINES                /* r11 <- # lines in cache  */
        mtctr   r11                              /* set loop counter         */

ic_dcloop:
        dccci   0,r10                            /* invalidate A/B cache lns */
        addi    r10,r10,DCACHE_NBYTES            /* bump to next line        */
        bdnz    ic_dcloop
        sync                                     /* ensure prev insts done   */
        isync

        /*--------------------------------------------------------------------+
        |  Enable Data Cache
        +--------------------------------------------------------------------*/
        lis     r10,DCACHE_ENABLE@h              /* r10 <- D-cache enable msk*/
        ori     r10,r10,DCACHE_ENABLE@l
        mtdccr  r10
        sync                                     /* ensure prev insts done   */
        isync

        blr
        function_epilog(initb_Dcache)


/******************************************************************************
|
| Routine:    INITB_ICACHE
|
| Purpose:    This routine will invalidate all data in the Instruction
|             Cache then enable I-Cache.
|
| Parameters: None.
|
| Returns:    None.
|
******************************************************************************/
        function_prolog(initb_Icache)
        /*--------------------------------------------------------------------+
        |  Invalidate Instruction Cache
        +--------------------------------------------------------------------*/
        li      r10,0                            /* r10 <- lines address     */
        iccci   0,r10                            /* invalidate all I-cache   */
        sync                                     /* ensure prev insts done   */
        isync

        /*--------------------------------------------------------------------+
        |  Enable Instruction Cache
        +--------------------------------------------------------------------*/
        lis     r10,ICACHE_ENABLE@h              /* r10 <- I-cache enable msk*/
        ori     r10,r10,ICACHE_ENABLE@l
        mticcr  r10
        sync                                     /* ensure prev insts done   */
        isync

        blr
        function_epilog(initb_Icache)

#if 0
/******************************************************************************
|
| Routine:    INITB_GET_CSPD
|
| Purpose:    Determine the CPU Core Speed.  The 13.5 Mhz Time Base
|             Counter (TBC) is used to measure a conditional branch
|             instruction.
|
| Parameters: R3 = Address of Bus Speed
|             R4 = Address of Core Speed
|
| Returns:    (R3) = >0: Bus Speed.
|                     0: Bus Speed not found in Look-Up Table.
|             (R4) = >0: Core Speed.
|                     0: Core Speed not found in Look-Up Table.
|
| Note:       1. This routine assumes the bdnz branch instruction takes
|                two instruction cycles to complete.
|             2. This routine must be called before interrupts are enabled.
|
******************************************************************************/
        function_prolog(initb_get_cspd)
        mflr    r0                               /* Save return address      */
        /*--------------------------------------------------------------------+
        |  Set-up timed loop
        +--------------------------------------------------------------------*/
        lis     r9,gcs_time_loop@h               /* r9  <- addr loop instr   */
        ori     r9,r9,gcs_time_loop@l
        lis     r10,GCS_LCNT@h                   /* r10 <- loop count        */
        ori     r10,r10,GCS_LCNT@l
        mtctr   r10                              /* ctr <- loop count        */
        lis     r11,STB_TIMERS_TBC@h             /* r11 <- TBC register addr */
        ori     r11,r11,STB_TIMERS_TBC@l
        li      r12,0                            /* r12 <- 0                 */

        /*--------------------------------------------------------------------+
        |  Cache timed-loop instruction
        +--------------------------------------------------------------------*/
        icbt    0,r9
        sync
        isync

        /*--------------------------------------------------------------------+
        |  Get number of 13.5 Mhz cycles to execute time-loop
        +--------------------------------------------------------------------*/
        stw     r12,0(r11)                       /* reset TBC                */
gcs_time_loop:
        bdnz+   gcs_time_loop                    /* force branch pred taken  */
        lwz     r5,0(r11)                        /* r5 <- num 13.5 Mhz ticks */
        li      r6,5                             /* LUT based on 1/5th the...*/
        divw    r5,r5,r6                         /*..loop count used         */
        sync
        isync

        /*--------------------------------------------------------------------+
        |  Look-up core speed based on TBC value
        +--------------------------------------------------------------------*/
        lis     r6,gcs_lookup_table@h            /* r6 <- pts at core spd LUT*/
        ori     r6,r6,gcs_lookup_table@l
        bl      gcs_cspd_lookup                  /* find core speed in LUT   */

        mtlr    r0                               /* set return address       */
        blr
        function_epilog(initb_get_cspd)

#endif
/*****************************************************************************+
| XXXX   XX   XX   XXXXXX  XXXXXXX  XXXXXX   XX   XX     XX    XXXX
|  XX    XXX  XX   X XX X   XX   X   XX  XX  XXX  XX    XXXX    XX
|  XX    XXXX XX     XX     XX X     XX  XX  XXXX XX   XX  XX   XX
|  XX    XX XXXX     XX     XXXX     XXXXX   XX XXXX   XX  XX   XX
|  XX    XX  XXX     XX     XX X     XX XX   XX  XXX   XXXXXX   XX
|  XX    XX   XX     XX     XX   X   XX  XX  XX   XX   XX  XX   XX  XX
| XXXX   XX   XX    XXXX   XXXXXXX  XXX  XX  XX   XX   XX  XX  XXXXXXX
+*****************************************************************************/
/******************************************************************************
|
| Routine:    HSMC_CR_WAIT
|
| Purpose:    Wait for the HSMC Control Register (bits 12-16) to be reset
|             after an auto-refresh, pre-charge or program mode register
|             command execution.
|
| Parameters: R3 = HSMC Control Register ID.
|                  0: HSMC0 CR0
|                  1: HSMC0 CR1
|                  2: HSMC1 CR0
|                  3: HSMC1 CR1
|
| Returns:    R3 = 0: Successful
|                 -1: Unsuccessful
|
******************************************************************************/
hsmc_cr_wait:

        li      r11,10                           /* r11 <- retry counter     */
        mtctr   r11                              /* set retry counter        */
        mr      r11,r3                           /* r11 <- HSMC CR reg id    */

hsmc_cr_rep:
        bdz     hsmc_cr_err                      /* branch if max retries hit*/

        /*--------------------------------------------------------------------+
        |  GET HSMCx_CRx value based on HSMC Control Register ID
        +--------------------------------------------------------------------*/
try_hsmc0_cr0:                                   /* CHECK IF ID=HSMC0 CR0 REG*/
        cmpwi   cr0,r11,0x0000
        bne     cr0,try_hsmc0_cr1
        mfdcr   r10,hsmc0_cr0                    /* r11 <- HSMC0 CR0 value   */
        b       hsmc_cr_read

try_hsmc0_cr1:                                   /* CHECK IF ID=HSMC0 CR1 REG*/
        cmpwi   cr0,r11,0x0001
        bne     cr0,try_hsmc1_cr0
        mfdcr   r10,hsmc0_cr1                    /* r10 <- HSMC0 CR1 value   */
        b       hsmc_cr_read

try_hsmc1_cr0:                                   /* CHECK IF ID=HSMC1 CR0 REG*/
        cmpwi   cr0,r11,0x0002
        bne     cr0,try_hsmc1_cr1
        mfdcr   r10,hsmc1_cr0                    /* r10 <- HSMC1 CR0 value   */
        b       hsmc_cr_read

try_hsmc1_cr1:                                   /* CHECK IF ID=HSMC1 CR1 REG*/
        cmpwi   cr0,r11,0x0003
        bne     cr0,hsmc_cr_err
        mfdcr   r10,hsmc1_cr1                    /* r10 <- HSMC1 CR1 value   */

        /*--------------------------------------------------------------------+
        |  Check if HSMC CR register was reset after command execution
        +--------------------------------------------------------------------*/
hsmc_cr_read:
        lis     r12,0x000F                       /* create "AND" mask        */
        ori     r12,r12,0x8000
        and.    r10,r10,r12                      /* r10 <- HSMC CR bits 12-16*/
        bne     cr0,hsmc_cr_rep                  /* wait for bits to reset   */
        li      r3,0                             /* set return code = success*/
        b       hsmc_cr_done

hsmc_cr_err:                                     /* ERROR: SDRAM didn't reset*/
        li      r3,-1                            /* set RC=unsuccessful      */

hsmc_cr_done:
        blr

#if 0
/******************************************************************************
|
| Routine:    GCS_CSPD_LOOKUP
|
| Purpose:    Uses the number of 13.5 Mhz clock ticks found after executing
|             the branch instruction time loop to look-up the CPU Core Speed
|             in the Core Speed Look-up Table.
|
| Parameters: R3 = Address of Bus Speed
|             R4 = Address of Core Speed
|             R5 = Number of 13.5 Mhz clock ticks found in time loop.
|             R6 = Pointer to Core-Speed Look-Up Table
|
| Returns:    (R3) = >0: Bus Speed.
|                     0: Bus Speed not found in Look-Up Table.
|             (R4) = >0: Core Speed.
|                     0: Core Speed not found in Look-Up Table.
|
| Note:       Core Speed = Bus Speed * Mult Factor (1-4x).
|
******************************************************************************/
gcs_cspd_lookup:

        li      r9,1                             /* r9 <- core speed mult    */
        /*--------------------------------------------------------------------+
        |  Get theoritical number 13.5 Mhz ticks for a given Bus Speed from
        |  Look-up Table.  Check all mult factors to determine if calculated
        |  value matches theoretical value (within a tolerance).
        +--------------------------------------------------------------------*/
gcs_cspd_loop:
        lwz     r10,0(r6)                        /* r10 <- no. ticks from LUT*/
        divw    r10,r10,r9                       /* r10 <- div mult (1-4x)   */
        subi    r11,r10,GCS_CTICK_TOL            /* r11 <- no. tks low range */
        addi    r12,r10,GCS_CTICK_TOL            /* r12 <- no. tks high range*/

        cmpw    cr0,r5,r11                       /* calc value within range? */
        blt     gcs_cspd_retry                   /* less than low range      */
        cmpw    cr0,r5,r12
        bgt     gcs_cspd_retry                   /* greater than high range  */
        b       gcs_cspd_fnd                     /* calc value within range  */

        /*--------------------------------------------------------------------+
        |  SO FAR CORE SPEED NOT FOUND: Check next mult factor
        +--------------------------------------------------------------------*/
gcs_cspd_retry:
        addi    r9,r9,1                          /* bump mult factor (1-4x)  */
        cmpwi   cr0,r9,GCS_NMULT
        ble     gcs_cspd_loop

        /*--------------------------------------------------------------------+
        |  SO FAR CORE SPEED NOT FOUND: Point at next Bus Speed in LUT
        +--------------------------------------------------------------------*/
        li      r9,1                             /* reset mult factor        */
        addi    r6,r6,GCS_TROW_BYTES             /* point at next table entry*/
        lwz     r10,0(r6)
        cmpwi   cr0,r10,0                        /* check for EOT flag       */
        bne     gcs_cspd_loop

        /*--------------------------------------------------------------------+
        |  COMPUTE CORE SPEED AND GET BUS SPEED FROM LOOK-UP TABLE
        +--------------------------------------------------------------------*/
gcs_cspd_fnd:
        lwz     r5,4(r6)                         /*  r5  <- Bus Speed in LUT */
        mullw   r6,r5,r9                         /*  r6  <- Core speed       */
        stw     r5,0(r3)                         /* (r3) <- Bus Speed        */
        stw     r6,0(r4)                         /* (r4) <- Core Speed       */

        blr
#endif