rw4_init_brd.s

linux内核源码

        |  Set Global SDRAM Controller to recommended default
        +--------------------------------------------------------------------*/
        lis     r10,0x6C00
        ori     r10,r10,0x0000
        mtdcr   hsmc0_gr,r10

        /*--------------------------------------------------------------------+
        |  Set HSMC0 Data Register to recommended default
        +--------------------------------------------------------------------*/
        lis     r10,0x0037
        ori     r10,r10,0x0000
        mtdcr   hsmc0_data,r10

        /*--------------------------------------------------------------------+
        |  Init HSMC0 Bank Register 0
        +--------------------------------------------------------------------*/
        lis     r10,HSMC0_BR0_VAL@h
        ori     r10,r10,HSMC0_BR0_VAL@l
        mtdcr   hsmc0_br0,r10

        /*--------------------------------------------------------------------+
        |  Init HSMC0 Bank Register 1
        +--------------------------------------------------------------------*/
        lis     r10,HSMC0_BR1_VAL@h
        ori     r10,r10,HSMC0_BR1_VAL@l
        mtdcr   hsmc0_br1,r10

        /*--------------------------------------------------------------------+
        |  Set HSMC0 Control Reg 0
        +--------------------------------------------------------------------*/
        lis     r10,0x8077                       /* PRECHARGE ALL DEVICE BKS */
        ori     r10,r10,0x0000
        mtdcr   hsmc0_cr0,r10
        li      r3,0x0000
        bl      hsmc_cr_wait                     /* wait for op completion   */
        cmpwi   cr0,r3,0x0000
        bne     cr0,hsmc0_err

        lis     r10,0x8078                       /* AUTO-REFRESH             */
        ori     r10,r10,0x0000
        mtdcr   hsmc0_cr0,r10
        li      r3,0x0000
        bl      hsmc_cr_wait                     /* wait for op completion   */
        cmpwi   cr0,r3,0x0000
        bne     cr0,hsmc0_err

        lis     r10,0x8070                       /* PROG MODE W/DATA REG VAL */
        ori     r10,r10,0x8000
        mtdcr   hsmc0_cr0,r10
        li      r3,0x0000
        bl      hsmc_cr_wait                     /* wait for op completion   */
        cmpwi   cr0,r3,0x0000
        bne     hsmc0_err

        /*--------------------------------------------------------------------+
        |  Set HSMC0 Control Reg 1
        +--------------------------------------------------------------------*/
        lis     r10,0x8077                       /* PRECHARGE ALL DEVICE BKS */
        ori     r10,r10,0x0000
        mtdcr   hsmc0_cr1,r10
        li      r3,0x0001
        bl      hsmc_cr_wait                     /* wait for op completion   */
        cmpwi   cr0,r3,0x0000
        bne     cr0,hsmc0_err

        lis     r10,0x8078                       /* AUTO-REFRESH             */
        ori     r10,r10,0x0000
        mtdcr   hsmc0_cr1,r10
        li      r3,0x0001
        bl      hsmc_cr_wait                     /* wait for op completion   */
        cmpwi   cr0,r3,0x0000
        bne     cr0,hsmc0_err

        lis     r10,0x8070                       /* PROG MODE W/DATA REG VAL */
        ori     r10,r10,0x8000
        mtdcr   hsmc0_cr1,r10
        li      r3,0x0001
        bl      hsmc_cr_wait                     /* wait for op completion   */
        cmpwi   cr0,r3,0x0000
        bne     cr0,hsmc0_err

        /*--------------------------------------------------------------------+
        |  Set HSMC0 Refresh Register
        +--------------------------------------------------------------------*/
        lis     r10,0x0FE1
        ori     r10,r10,0x0000
        mtdcr   hsmc0_crr,r10
        li      r3,0

hsmc0_err:
        mtlr    r0
        blr
        function_epilog(initb_hsmc0)


/******************************************************************************
|
| Routine:    INITB_HSMC1.
|
| Purpose:    Initialize the HSMC1 Registers for SDRAM
| Parameters: None.
| Returns:    R3 =  0: Successful
|                = -1: Unsuccessful, SDRAM did not reset properly.
|
******************************************************************************/
        function_prolog(initb_hsmc1)
        mflr    r0                               /* Save return addr         */

        /*--------------------------------------------------------------------+
        |  Set Global SDRAM Controller to recommended default
        +--------------------------------------------------------------------*/
        lis     r10,0x6C00
        ori     r10,r10,0x0000
        mtdcr   hsmc1_gr,r10

        /*--------------------------------------------------------------------+
        |  Set HSMC1 Data Register to recommended default
        +--------------------------------------------------------------------*/
        lis     r10,0x0037
        ori     r10,r10,0x0000
        mtdcr   hsmc1_data,r10

        /*--------------------------------------------------------------------+
        |  Init HSMC1 Bank Register 0
        +--------------------------------------------------------------------*/
        lis     r10,HSMC1_BR0_VAL@h
        ori     r10,r10,HSMC1_BR0_VAL@l
        mtdcr   hsmc1_br0,r10

        /*--------------------------------------------------------------------+
        |  Init HSMC1 Bank Register 1
        +--------------------------------------------------------------------*/
        lis     r10,HSMC1_BR1_VAL@h
        ori     r10,r10,HSMC1_BR1_VAL@l
        mtdcr   hsmc1_br1,r10

        /*--------------------------------------------------------------------+
        |  Set HSMC1 Control Reg 0
        +--------------------------------------------------------------------*/
        lis     r10,0x8077                       /* PRECHARGE ALL DEVICE BANKS    */
        ori     r10,r10,0x0000
        mtdcr   hsmc1_cr0,r10
        li      r3,0x0002
        bl      hsmc_cr_wait                     /* wait for operation completion */
        cmpwi   cr0,r3,0x0000
        bne     hsmc1_err

        lis     r10,0x8078                       /* AUTO-REFRESH                  */
        ori     r10,r10,0x0000
        mtdcr   hsmc1_cr0,r10
        li      r3,0x0002
        bl      hsmc_cr_wait                     /* wait for operation completion */
        cmpwi   cr0,r3,0x0000
        bne     hsmc1_err

        lis     r10,0x8070                       /* PROGRAM MODE W/DATA REG VALUE */
        ori     r10,r10,0x8000
        mtdcr   hsmc1_cr0,r10
        li      r3,0x0002
        bl      hsmc_cr_wait                     /* wait for operation completion */
        cmpwi   cr0,r3,0x0000
        bne     hsmc1_err

        /*--------------------------------------------------------------------+
        |  Set HSMC1 Control Reg 1
        +--------------------------------------------------------------------*/
        lis     r10,0x8077                       /* PRECHARGE ALL DEVICE BKS */
        ori     r10,r10,0x0000
        mtdcr   hsmc1_cr1,r10
        li      r3,0x0003
        bl      hsmc_cr_wait                     /* wait for op completion   */
        cmpwi   cr0,r3,0x0000
        bne     hsmc1_err

        lis     r10,0x8078                       /* AUTO-REFRESH             */
        ori     r10,r10,0x0000
        mtdcr   hsmc1_cr1,r10
        li      r3,0x0003
        bl      hsmc_cr_wait                     /* wait for op completion   */
        cmpwi   cr0,r3,0x0000
        bne     hsmc1_err

        lis     r10,0x8070                       /* PROG MODE W/DATA REG VAL */
        ori     r10,r10,0x8000
        mtdcr   hsmc1_cr1,r10
        li      r3,0x0003
        bl      hsmc_cr_wait                     /* wait for op completion   */
        cmpwi   cr0,r3,0x0000
        bne     hsmc1_err

        /*--------------------------------------------------------------------+
        |  Set HSMC1 Refresh Register
        +--------------------------------------------------------------------*/
        lis     r10,0x0FE1
        ori     r10,r10,0x0000
        mtdcr   hsmc1_crr,r10
        xor     r3,r3,r3

hsmc1_err:
        mtlr    r0
        blr
        function_epilog(initb_hsmc1)


/******************************************************************************
|
| Routine:    INITB_CACHE
|
| Purpose:    This routine will enable Data and Instruction Cache.
|             The Data Cache is an 8K two-way set associative and the
|             Instruction Cache is an 16K two-way set associative cache.
|
| Parameters: None.
|
| Returns:    None.
|
******************************************************************************/
        function_prolog(initb_cache)
        mflr    r0                               /* Save return addr         */

        bl      initb_Dcache                     /* enable D-Cache           */
        bl      initb_Icache                     /* enable I-Cache           */

        mtlr    r0
        blr
       function_epilog(initb_cache)


/******************************************************************************
|
| Routine:    INITB_DCACHE
|
| Purpose:    This routine will invalidate all data in the Data Cache and
|             then enable D-Cache.  If cache is enabled already, the D-Cache
|             will be flushed before the data is invalidated.
|
| Parameters: None.
|
| Returns:    None.
|
******************************************************************************/
        function_prolog(initb_Dcache)
        /*--------------------------------------------------------------------+
        |  Flush Data Cache if enabled
        +--------------------------------------------------------------------*/
        mfdccr  r10                              /* r10 <- DCCR              */
        isync                                    /* ensure prev insts done   */
        cmpwi   r10,0x00
        beq     ic_dcinv                         /* D-cache off, invalidate  */

        /*--------------------------------------------------------------------+
        |  Data Cache enabled, force known memory addresses to be Cached
        +--------------------------------------------------------------------*/
        lis     r10,HSMC0_BR0_VAL@h              /* r10 <- first memory loc  */
        andis.  r10,r10,0xFFF0
        li      r11,DCACHE_NLINES                /* r11 <- # A-way addresses */
        addi    r11,r11,DCACHE_NLINES            /* r11 <- # B-way addresses */
        mtctr   r11                              /* set loop counter         */

ic_dcload:
        lwz     r12,0(r10)                       /* force cache of address   */
        addi    r10,r10,DCACHE_NBYTES            /* r10 <- next memory loc   */
        bdnz    ic_dcload
        sync                                     /* ensure prev insts done   */
        isync

        /*--------------------------------------------------------------------+
        |  Flush the known memory addresses from Cache
        +--------------------------------------------------------------------*/
        lis     r10,HSMC0_BR0_VAL@h              /* r10 <- first memory loc  */
        andis.  r10,r10,0xFFF0
        mtctr   r11                              /* set loop counter         */

ic_dcflush:
        dcbf    0,r10                            /* flush D-cache line       */
        addi    r10,r10,DCACHE_NBYTES            /* r10 <- next memory loc   */
        bdnz    ic_dcflush
        sync                                     /* ensure prev insts done   */
        isync

        /*--------------------------------------------------------------------+
        |  Disable then invalidate Data Cache