rw4_init_brd.s

linux内核源码

        |  Set EBIU0 Bank 5
        +--------------------------------------------------------------------*/
        lis     r10,EBIU0_BRCR5_VAL@h
        ori     r10,r10,EBIU0_BRCR5_VAL@l
        mtdcr   ebiu0_brcr5,r10
        lis     r10,EBIU0_BRCRH5_VAL@h
        ori     r10,r10,EBIU0_BRCRH5_VAL@l
        mtdcr   ebiu0_brcrh5,r10

        /*--------------------------------------------------------------------+
        |  Set EBIU0 Bank 6
        +--------------------------------------------------------------------*/
        lis     r10,EBIU0_BRCR6_VAL@h
        ori     r10,r10,EBIU0_BRCR6_VAL@l
        mtdcr   ebiu0_brcr6,r10
        lis     r10,EBIU0_BRCRH6_VAL@h
        ori     r10,r10,EBIU0_BRCRH6_VAL@l
        mtdcr   ebiu0_brcrh6,r10

        /*--------------------------------------------------------------------+
        |  Set EBIU0 Bank 7
        +--------------------------------------------------------------------*/
        lis     r10,EBIU0_BRCR7_VAL@h
        ori     r10,r10,EBIU0_BRCR7_VAL@l
        mtdcr   ebiu0_brcr7,r10
        lis     r10,EBIU0_BRCRH7_VAL@h
        ori     r10,r10,EBIU0_BRCRH7_VAL@l
        mtdcr   ebiu0_brcrh7,r10

        blr
        function_epilog(initb_ebiu0)


/******************************************************************************
|
| Routine:    INITB_CONFIG
|
| Purpose:    Configure the Vesta Evaluation Board.  The following items
|             will be configured:
|               1.  Cross-Bar Switch.
|               2.  Chip Interconnect.
|               3.  Clear/reset key PPC registers.
|               4.  Xilinx and GPIO Registers.
|
| Returns:    None.
|
******************************************************************************/
        function_prolog(initb_config)
        /*--------------------------------------------------------------------+
        |  Init CROSS-BAR SWITCH
        +--------------------------------------------------------------------*/
        lis     r10,CBS0_CR_VAL@h                /* r10 <- CBS Cntl Reg val  */
        ori     r10,r10,CBS0_CR_VAL@l
        mtdcr   cbs0_cr,r10

        /*--------------------------------------------------------------------+
        |  Init Chip-Interconnect (CIC) Registers
        +--------------------------------------------------------------------*/
        lis     r10,CIC0_CR_VAL@h                /* r10 <- CIC Cntl Reg val  */
        ori     r10,r10,CIC0_CR_VAL@l
        mtdcr   cic0_cr,r10

        lis     r10,CIC0_SEL3_VAL@h              /* r10 <- CIC SEL3 Reg val  */
        ori     r10,r10,CIC0_SEL3_VAL@l
        mtdcr   cic0_sel3,r10

        lis     r10,CIC0_VCR_VAL@h               /* r10 <- CIC Vid C-Reg val */
        ori     r10,r10,CIC0_VCR_VAL@l
        mtdcr   cic0_vcr,r10

        /*--------------------------------------------------------------------+
        | Clear SGR and DCWR
        +--------------------------------------------------------------------*/
        li      r10,0x0000
        mtspr   sgr,r10
        mtspr   dcwr,r10

        /*--------------------------------------------------------------------+
        | Clear/set up some machine state registers.
        +--------------------------------------------------------------------*/
        li      r10,0x0000                       /* r10 <- 0                 */
        mtdcr   ebiu0_besr,r10                   /* clr Bus Err Syndrome Reg */
        mtspr   esr,r10                          /* clr Exceptn Syndrome Reg */
        mttcr   r10                              /* timer control register   */

        mtdcr   uic0_er,r10                      /* disable all interrupts   */

	/* UIC_IIC0 | UIC_IIC1 | UIC_U0 | UIC_IR_RCV | UIC_IR_XMIT */
	lis	r10,    0x00600e00@h
	ori	r10,r10,0x00600e00@l
	mtdcr	uic0_pr,r10

	li	r10,0x00000020			/* UIC_EIR1 */
	mtdcr	uic0_tr,r10

        lis     r10,0xFFFF                       /* r10 <- 0xFFFFFFFF        */
        ori     r10,r10,0xFFFF                   /*                          */
        mtdbsr  r10                              /* clear/reset the dbsr     */
        mtdcr   uic0_sr,r10                      /* clear pending interrupts */

        li      r10,0x1000                       /* set Machine Exception bit*/
        oris    r10,r10,0x2                      /* set Criticl Exception bit*/
        mtmsr   r10                              /* change MSR               */

        /*--------------------------------------------------------------------+
        |  Clear XER.
        +--------------------------------------------------------------------*/
        li      r10,0x0000
        mtxer   r10

        /*--------------------------------------------------------------------+
        |  Init GPIO0 Registers
        +--------------------------------------------------------------------*/
        lis     r10,    STB_GPIO0_TC@h           /* Three-state control      */
        ori     r10,r10,STB_GPIO0_TC@l
        lis     r11,    GPIO0_TC_VAL@h
        ori     r11,r11,GPIO0_TC_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_OS_0_31@h      /* output select 0-31       */
        ori     r10,r10,STB_GPIO0_OS_0_31@l
        lis     r11,    GPIO0_OS_0_31_VAL@h
        ori     r11,r11,GPIO0_OS_0_31_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_OS_32_63@h     /* output select 32-63      */
        ori     r10,r10,STB_GPIO0_OS_32_63@l
        lis     r11,    GPIO0_OS_32_63_VAL@h
        ori     r11,r11,GPIO0_OS_32_63_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_TS_0_31@h      /* three-state select 0-31  */
        ori     r10,r10,STB_GPIO0_TS_0_31@l
        lis     r11,    GPIO0_TS_0_31_VAL@h
        ori     r11,r11,GPIO0_TS_0_31_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_TS_32_63@h     /* three-state select 32-63 */
        ori     r10,r10,STB_GPIO0_TS_32_63@l
        lis     r11,    GPIO0_TS_32_63_VAL@h
        ori     r11,r11,GPIO0_TS_32_63_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_OD@h           /* open drain               */
        ori     r10,r10,STB_GPIO0_OD@l
        lis     r11,    GPIO0_OD_VAL@h
        ori     r11,r11,GPIO0_OD_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_IS_1_0_31@h    /* input select 1, 0-31     */
        ori     r10,r10,STB_GPIO0_IS_1_0_31@l
        lis     r11,    GPIO0_IS_1_0_31_VAL@h
        ori     r11,r11,GPIO0_IS_1_0_31_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_IS_1_32_63@h   /* input select 1, 32-63    */
        ori     r10,r10,STB_GPIO0_IS_1_32_63@l
        lis     r11,    GPIO0_IS_1_32_63_VAL@h
        ori     r11,r11,GPIO0_IS_1_32_63_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_IS_2_0_31@h    /* input select 2, 0-31     */
        ori     r10,r10,STB_GPIO0_IS_2_0_31@l
        lis     r11,    GPIO0_IS_2_0_31_VAL@h
        ori     r11,r11,GPIO0_IS_2_0_31_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_IS_2_32_63@h   /* input select 2, 32-63    */
        ori     r10,r10,STB_GPIO0_IS_2_32_63@l
        lis     r11,    GPIO0_IS_2_32_63_VAL@h
        ori     r11,r11,GPIO0_IS_2_32_63_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_IS_3_0_31@h    /* input select 3, 0-31     */
        ori     r10,r10,STB_GPIO0_IS_3_0_31@l
        lis     r11,    GPIO0_IS_3_0_31_VAL@h
        ori     r11,r11,GPIO0_IS_3_0_31_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_IS_3_32_63@h   /* input select 3, 32-63    */
        ori     r10,r10,STB_GPIO0_IS_3_32_63@l
        lis     r11,    GPIO0_IS_3_32_63_VAL@h
        ori     r11,r11,GPIO0_IS_3_32_63_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_SS_1@h         /* sync select 1            */
        ori     r10,r10,STB_GPIO0_SS_1@l
        lis     r11,    GPIO0_SS_1_VAL@h
        ori     r11,r11,GPIO0_SS_1_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_SS_2@h         /* sync select 2            */
        ori     r10,r10,STB_GPIO0_SS_2@l
        lis     r11,    GPIO0_SS_2_VAL@h
        ori     r11,r11,GPIO0_SS_2_VAL@l
        stw     r11,0(r10)

        lis     r10,    STB_GPIO0_SS_3@h         /* sync select 3            */
        ori     r10,r10,STB_GPIO0_SS_3@l
        lis     r11,    GPIO0_SS_3_VAL@h
        ori     r11,r11,GPIO0_SS_3_VAL@l
        stw     r11,0(r10)

        /*--------------------------------------------------------------------+
        |  Init Xilinx #1 Registers
        +--------------------------------------------------------------------*/
        lis     r10,    STB_XILINX1_REG0@h       /* init Xilinx1 Reg 0       */
        ori     r10,r10,STB_XILINX1_REG0@l
        li      r11,XILINX1_R0_VAL
        sth     r11,0(r10)

        lis     r10,    STB_XILINX1_REG1@h       /* init Xilinx1 Reg 1       */
        ori     r10,r10,STB_XILINX1_REG1@l
        li      r11,XILINX1_R1_VAL
        sth     r11,0(r10)

        lis     r10,    STB_XILINX1_REG2@h       /* init Xilinx1 Reg 2       */
        ori     r10,r10,STB_XILINX1_REG2@l
        li      r11,XILINX1_R2_VAL
        sth     r11,0(r10)

        lis     r10,    STB_XILINX1_REG3@h       /* init Xilinx1 Reg 3       */
        ori     r10,r10,STB_XILINX1_REG3@l
        li      r11,XILINX1_R3_VAL
        sth     r11,0(r10)

        lis     r10,    STB_XILINX1_REG4@h       /* init Xilinx1 Reg 4       */
        ori     r10,r10,STB_XILINX1_REG4@l
        li      r11,XILINX1_R4_VAL
        sth     r11,0(r10)

        lis     r10,    STB_XILINX1_REG5@h       /* init Xilinx1 Reg 5       */
        ori     r10,r10,STB_XILINX1_REG5@l
        li      r11,XILINX1_R5_VAL
        sth     r11,0(r10)

        lis     r10,    STB_XILINX1_REG6@h       /* init Xilinx1 Reg 6       */
        ori     r10,r10,STB_XILINX1_REG6@l
        li      r11,XILINX1_R6_VAL
        sth     r11,0(r10)

        lis     r10,    STB_XILINX1_FLUSH@h      /* latch registers in Xilinx*/
        ori     r10,r10,STB_XILINX1_FLUSH@l
        li      r11,0x0000
        sth     r11,0(r10)

        /*--------------------------------------------------------------------+
        |  Init Xilinx #2 Registers
        +--------------------------------------------------------------------*/
        lis     r10,    STB_XILINX2_REG0@h       /* init Xilinx2 Reg 0       */
        ori     r10,r10,STB_XILINX2_REG0@l
        li      r11,XILINX2_R0_VAL
        sth     r11,0(r10)

        lis     r10,    STB_XILINX2_REG1@h       /* init Xilinx2 Reg 1       */
        ori     r10,r10,STB_XILINX2_REG1@l
        li      r11,XILINX2_R1_VAL
        sth     r11,0(r10)

        lis     r10,    STB_XILINX2_REG2@h       /* init Xilinx2 Reg 2       */
        ori     r10,r10,STB_XILINX2_REG2@l
        li      r11,XILINX2_R2_VAL
        sth     r11,0(r10)

        blr
        function_epilog(initb_config)


/******************************************************************************
|
| Routine:    INITB_HSMC0.
|
| Purpose:    Initialize the HSMC0 Registers for SDRAM
| Parameters: None.
| Returns:    R3 =  0: Successful
|                = -1: Unsuccessful, SDRAM did not reset properly.
|
******************************************************************************/
        function_prolog(initb_hsmc0)
        mflr    r0                               /* Save return addr         */

        /*--------------------------------------------------------------------+