rw4_init_brd.s

linux内核源码

/*----------------------------------------------------------------------------+
|       This source code has been made available to you by IBM on an AS-IS
|       basis.  Anyone receiving this source is licensed under IBM
|       copyrights to use it in any way he or she deems fit, including
|       copying it, modifying it, compiling it, and redistributing it either
|       with or without modifications.  No license under IBM patents or
|       patent applications is to be implied by the copyright license.
|
|       Any user of this software should understand that IBM cannot provide
|       technical support for this software and will not be responsible for
|       any consequences resulting from the use of this software.
|
|       Any person who transfers this source code or any derivative work
|       must include the IBM copyright notice, this paragraph, and the
|       preceding two paragraphs in the transferred software.
|
|       COPYRIGHT   I B M   CORPORATION 1997
|       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
| Author:    Tony J. Cerreto
| Component: BSPS
| File:      init_brd.s
| Purpose:   Vesta Evaluation Board initialization subroutines.  The following
|            routines are available:
|              1. INITB_EBIU0:    Initialize EBIU0.
|              2. INITB_CONFIG:   Configure board.
|              3. INITB_HSMC0:    Initialize HSMC0 (SDRAM).
|              4. INITB_HSMC1:    Initialize HSMC1 (SDRAM).
|              5. INITB_CACHE:    Initialize Data and Instruction Cache.
|              6. INITB_DCACHE:   Initialize Data Cache.
|              7. INITB_ICACHE:   Initialize Instruction Cache.
|              8. INITB_GET_CSPD: Get CPU Speed (Bus Speed and Processor Speed)
|
| Changes:
| Date:      Author  Comment:
| ---------  ------  --------
| 01-Mar-00  tjc     Created
| 04-Mar-00  jfh     Modified CIC_SEL3_VAL to support 1284 (Mux3 & GPIO 21-28)
| 04-Mar-00  jfh     Modified XILINIX Reg 0 to support 1284 (Mux3 & GPIO 21-28)
| 04-Mar-00  jfh     Modified XILINIX Reg 1 to support 1284 (Mux3 & GPIO 21-28)
| 04-Mar-00  jfh     Modified XILINIX Reg 4 to support 1284 (Mux3 & GPIO 21-28)
| 19-May-00  rlb     Relcoated HSMC0 to 0x1F000000 to support 32MB of contiguous
|                    SDRAM space.  Changed cache ctl regs to reflect this.
| 22-May-00  tjc     Changed initb_get_cspd interface and eliminated
|                    initb_get_bspd routines.
| 26-May-00  tjc     Added two nop instructions after all mtxxx/mfxxx
|                    instructions due to PPC405 bug.
+----------------------------------------------------------------------------*/
#define VESTA
#include "ppc_40x.h"
#include "stb.h"

/*----------------------------------------------------------------------------+
| BOARD CONFIGURATION DEFINES
+----------------------------------------------------------------------------*/
#define CBS0_CR_VAL          0x00000002          /* CBS control reg value    */
#define CIC0_CR_VAL          0xD0800448          /* CIC control reg value    */
#define CIC0_SEL3_VAL        0x11500000          /* CIC select 3 reg value   */
#define CIC0_VCR_VAL         0x00631700          /* CIC video cntl reg value */

/*----------------------------------------------------------------------------+
| EBIU0 BANK REGISTERS DEFINES
+----------------------------------------------------------------------------*/
#define EBIU0_BRCRH0_VAL     0x00000000          /* BR High 0 (Extension Reg)*/
#define EBIU0_BRCRH1_VAL     0x00000000          /* BR High 1 (Extension Reg)*/
#define EBIU0_BRCRH2_VAL     0x40000000          /* BR High 2 (Extension Reg)*/
#define EBIU0_BRCRH3_VAL     0x40000000          /* BR High 3 (Extension Reg)*/
#define EBIU0_BRCRH4_VAL     0x00000000          /* BR High 4 (Extension Reg)*/
#define EBIU0_BRCRH5_VAL     0x00000000          /* BR High 5 (Extension Reg)*/
#define EBIU0_BRCRH6_VAL     0x00000000          /* BR High 6 (Extension Reg)*/
#define EBIU0_BRCRH7_VAL     0x40000000          /* BR High 7 (Extension Reg)*/

#define EBIU0_BRCR0_VAL      0xFC58BFFE          /* BR 0: 16 bit Flash  4 MB */
#define EBIU0_BRCR1_VAL      0xFF00BFFE          /* BR 1: Ext Connector 1 MB */
#if 1
#define EBIU0_BRCR2_VAL      0x207CFFBE          /* BR 2: Xilinx        8 MB */
                                                 /* twt == 0x3f              */
#else
#define EBIU0_BRCR2_VAL      0x207CCFBE          /* BR 2: Xilinx        8 MB */
                                                 /* twt == 0x0f              */
#endif
#define EBIU0_BRCR3_VAL      0x407CBFBE          /* BR 3: IDE Drive     8 MB */
#define EBIU0_BRCR4_VAL      0xFF00BFFF          /* BR 4: Disabled.     0 MB */
#define EBIU0_BRCR5_VAL      0xFF00BFFF          /* BR 5: Disabled.     0 MB */
#define EBIU0_BRCR6_VAL      0xFF00BFFF          /* BR 6: Disabled.     0 MB */
#define EBIU0_BRCR7_VAL      0xCE3F0003          /* BR 7: Line Mode DMA 2 MB */

/*----------------------------------------------------------------------------+
| GPIO DEFINES
+----------------------------------------------------------------------------*/
#define STB_GPIO0_OUTPUT     (STB_GPIO0_BASE_ADDRESS+ 0x00)
#define STB_GPIO0_TC         (STB_GPIO0_BASE_ADDRESS+ 0x04)
#define STB_GPIO0_OS_0_31    (STB_GPIO0_BASE_ADDRESS+ 0x08)
#define STB_GPIO0_OS_32_63   (STB_GPIO0_BASE_ADDRESS+ 0x0C)
#define STB_GPIO0_TS_0_31    (STB_GPIO0_BASE_ADDRESS+ 0x10)
#define STB_GPIO0_TS_32_63   (STB_GPIO0_BASE_ADDRESS+ 0x14)
#define STB_GPIO0_OD         (STB_GPIO0_BASE_ADDRESS+ 0x18)
#define STB_GPIO0_INPUT      (STB_GPIO0_BASE_ADDRESS+ 0x1C)
#define STB_GPIO0_R1         (STB_GPIO0_BASE_ADDRESS+ 0x20)
#define STB_GPIO0_R2         (STB_GPIO0_BASE_ADDRESS+ 0x24)
#define STB_GPIO0_R3         (STB_GPIO0_BASE_ADDRESS+ 0x28)
#define STB_GPIO0_IS_1_0_31  (STB_GPIO0_BASE_ADDRESS+ 0x30)
#define STB_GPIO0_IS_1_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x34)
#define STB_GPIO0_IS_2_0_31  (STB_GPIO0_BASE_ADDRESS+ 0x38)
#define STB_GPIO0_IS_2_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x3C)
#define STB_GPIO0_IS_3_0_31  (STB_GPIO0_BASE_ADDRESS+ 0x40)
#define STB_GPIO0_IS_3_32_63 (STB_GPIO0_BASE_ADDRESS+ 0x44)
#define STB_GPIO0_SS_1       (STB_GPIO0_BASE_ADDRESS+ 0x50)
#define STB_GPIO0_SS_2       (STB_GPIO0_BASE_ADDRESS+ 0x54)
#define STB_GPIO0_SS_3       (STB_GPIO0_BASE_ADDRESS+ 0x58)

#define GPIO0_TC_VAL         0x0C020004          /* three-state control val  */
#define GPIO0_OS_0_31_VAL    0x51A00004          /* output select 0-31  val  */
#define GPIO0_OS_32_63_VAL   0x0000002F          /* output select 32-63 val  */
#define GPIO0_TS_0_31_VAL    0x51A00000          /* three-state sel 0-31  val*/
#define GPIO0_TS_32_63_VAL   0x0000000F          /* three-state sel 32-63 val*/
#define GPIO0_OD_VAL         0xC0000004          /* open drain val           */
#define GPIO0_IS_1_0_31_VAL  0x50000151          /* input select 1 0-31  val */
#define GPIO0_IS_1_32_63_VAL 0x00000000          /* input select 1 32-63 val */
#define GPIO0_IS_2_0_31_VAL  0x00000000          /* input select 2 0-31  val */
#define GPIO0_IS_2_32_63_VAL 0x00000000          /* input select 2 32-63 val */
#define GPIO0_IS_3_0_31_VAL  0x00000440          /* input select 3 0-31  val */
#define GPIO0_IS_3_32_63_VAL 0x00000000          /* input select 3 32-63 val */
#define GPIO0_SS_1_VAL       0x00000000          /* sync select 1 val        */
#define GPIO0_SS_2_VAL       0x00000000          /* sync select 2 val        */
#define GPIO0_SS_3_VAL       0x00000000          /* sync select 3 val        */

/*----------------------------------------------------------------------------+
| XILINX DEFINES
+----------------------------------------------------------------------------*/
#define STB_XILINX_LED       (STB_FPGA_BASE_ADDRESS+ 0x0100)
#define STB_XILINX1_REG0     (STB_FPGA_BASE_ADDRESS+ 0x40000)
#define STB_XILINX1_REG1     (STB_FPGA_BASE_ADDRESS+ 0x40002)
#define STB_XILINX1_REG2     (STB_FPGA_BASE_ADDRESS+ 0x40004)
#define STB_XILINX1_REG3     (STB_FPGA_BASE_ADDRESS+ 0x40006)
#define STB_XILINX1_REG4     (STB_FPGA_BASE_ADDRESS+ 0x40008)
#define STB_XILINX1_REG5     (STB_FPGA_BASE_ADDRESS+ 0x4000A)
#define STB_XILINX1_REG6     (STB_FPGA_BASE_ADDRESS+ 0x4000C)
#define STB_XILINX1_ID       (STB_FPGA_BASE_ADDRESS+ 0x4000E)
#define STB_XILINX1_FLUSH    (STB_FPGA_BASE_ADDRESS+ 0x4000E)
#define STB_XILINX2_REG0     (STB_FPGA_BASE_ADDRESS+ 0x80000)
#define STB_XILINX2_REG1     (STB_FPGA_BASE_ADDRESS+ 0x80002)
#define STB_XILINX2_REG2     (STB_FPGA_BASE_ADDRESS+ 0x80004)

#define XILINX1_R0_VAL       0x2440              /* Xilinx 1 Register 0 Val  */
#define XILINX1_R1_VAL       0x0025              /* Xilinx 1 Register 1 Val  */
#define XILINX1_R2_VAL       0x0441              /* Xilinx 1 Register 2 Val  */
#define XILINX1_R3_VAL       0x0008              /* Xilinx 1 Register 3 Val  */
#define XILINX1_R4_VAL       0x0100              /* Xilinx 1 Register 4 Val  */
#define XILINX1_R5_VAL       0x6810              /* Xilinx 1 Register 5 Val  */
#define XILINX1_R6_VAL       0x0000              /* Xilinx 1 Register 6 Val  */
#if 0
#define XILINX2_R0_VAL       0x0008              /* Xilinx 2 Register 0 Val  */
#define XILINX2_R1_VAL       0x0000              /* Xilinx 2 Register 1 Val  */
#else
#define XILINX2_R0_VAL       0x0018              /* disable IBM IrDA RxD     */
#define XILINX2_R1_VAL       0x0008              /* enable SICC MAX chip     */
#endif
#define XILINX2_R2_VAL       0x0000              /* Xilinx 2 Register 2 Val  */

/*----------------------------------------------------------------------------+
| HSMC BANK REGISTERS DEFINES
+----------------------------------------------------------------------------*/
#ifdef SDRAM16MB
#define HSMC0_BR0_VAL        0x000D2D55          /* 0x1F000000-007FFFFF R/W  */
#define HSMC0_BR1_VAL        0x008D2D55          /* 0x1F800000-1FFFFFFF R/W  */
#else
#define HSMC0_BR0_VAL        0x1F0D2D55          /* 0x1F000000-007FFFFF R/W  */
#define HSMC0_BR1_VAL        0x1F8D2D55          /* 0x1F800000-1FFFFFFF R/W  */
#endif
#define HSMC1_BR0_VAL        0xA00D2D55          /* 0xA0000000-A07FFFFF R/W  */
#define HSMC1_BR1_VAL        0xA08D2D55          /* 0xA0800000-A0FFFFFF R/W  */

/*----------------------------------------------------------------------------+
| CACHE DEFINES
+----------------------------------------------------------------------------*/
#define DCACHE_NLINES               128          /* no. D-cache lines        */
#define DCACHE_NBYTES                32          /* no. bytes/ D-cache line  */
#define ICACHE_NLINES               256          /* no. I-cache lines        */
#define ICACHE_NBYTES                32          /* no. bytes/ I-cache line  */
#ifdef SDRAM16MB
#define DCACHE_ENABLE        0x80000000          /* D-cache regions to enable*/
#define ICACHE_ENABLE        0x80000001          /* I-cache regions to enable*/
#else
#define DCACHE_ENABLE        0x18000000          /* D-cache regions to enable*/
#define ICACHE_ENABLE        0x18000001          /* I-cache regions to enable*/
#endif

/*----------------------------------------------------------------------------+
| CPU CORE SPEED CALCULATION DEFINES
+----------------------------------------------------------------------------*/
#define GCS_LCNT                 500000          /* CPU speed loop count     */
#define GCS_TROW_BYTES                8          /* no. bytes in table row   */
#define GCS_CTICK_TOL               100          /* allowable clock tick tol */
#define GCS_NMULT                     4          /* no. of core speed mults  */

        /*--------------------------------------------------------------------+
        |        No. 13.5Mhz
        |        Clock Ticks
        |        based on a
        |        loop count    Bus
        |        of 100,000    Speed
        +--------------------------------------------------------------------*/
gcs_lookup_table:
        .int           50000,  54000000          /* 54.0 Mhz                 */
        .int           66667,  40500000          /* 40.5 Mhz                 */
        .int           54545,  49500000          /* 49.5 Mhz                 */
        .int           46154,  58500000          /* 58.5 Mhz                 */
        .int               0,         0          /* end of table flag        */


/*****************************************************************************+
| XXXXXXX  XXX XXX   XXXXXX  XXXXXXX  XXXXXX   XX   XX     XX    XXXX
|  XX   X   XX XX    X XX X   XX   X   XX  XX  XXX  XX    XXXX    XX
|  XX X      XXX       XX     XX X     XX  XX  XXXX XX   XX  XX   XX
|  XXXX       X        XX     XXXX     XXXXX   XX XXXX   XX  XX   XX
|  XX X      XXX       XX     XX X     XX XX   XX  XXX   XXXXXX   XX
|  XX   X   XX XX      XX     XX   X   XX  XX  XX   XX   XX  XX   XX  XX
| XXXXXXX  XXX XXX    XXXX   XXXXXXX  XXX  XX  XX   XX   XX  XX  XXXXXXX
+*****************************************************************************/
/******************************************************************************
|
| Routine:    INITB_EBIU0.
|
| Purpose:    Initialize all the EBIU0 Bank Registers
| Parameters: None.
| Returns:    None.
|
******************************************************************************/
        function_prolog(initb_ebiu0)
        /*--------------------------------------------------------------------+
        |  Set EBIU0 Bank 0
        +--------------------------------------------------------------------*/
        lis     r10,EBIU0_BRCR0_VAL@h
        ori     r10,r10,EBIU0_BRCR0_VAL@l
        mtdcr   ebiu0_brcr0,r10
        lis     r10,EBIU0_BRCRH0_VAL@h
        ori     r10,r10,EBIU0_BRCRH0_VAL@l
        mtdcr   ebiu0_brcrh0,r10

        /*--------------------------------------------------------------------+
        |  Set EBIU0 Bank 1
        +--------------------------------------------------------------------*/
        lis     r10,EBIU0_BRCR1_VAL@h
        ori     r10,r10,EBIU0_BRCR1_VAL@l
        mtdcr   ebiu0_brcr1,r10
        lis     r10,EBIU0_BRCRH1_VAL@h
        ori     r10,r10,EBIU0_BRCRH1_VAL@l
        mtdcr   ebiu0_brcrh1,r10

        /*--------------------------------------------------------------------+
        |  Set EBIU0 Bank 2
        +--------------------------------------------------------------------*/
        lis     r10,EBIU0_BRCR2_VAL@h
        ori     r10,r10,EBIU0_BRCR2_VAL@l
        mtdcr   ebiu0_brcr2,r10
        lis     r10,EBIU0_BRCRH2_VAL@h
        ori     r10,r10,EBIU0_BRCRH2_VAL@l
        mtdcr   ebiu0_brcrh2,r10

        /*--------------------------------------------------------------------+
        |  Set EBIU0 Bank 3
        +--------------------------------------------------------------------*/
        lis     r10,EBIU0_BRCR3_VAL@h
        ori     r10,r10,EBIU0_BRCR3_VAL@l
        mtdcr   ebiu0_brcr3,r10
        lis     r10,EBIU0_BRCRH3_VAL@h
        ori     r10,r10,EBIU0_BRCRH3_VAL@l
        mtdcr   ebiu0_brcrh3,r10

        /*--------------------------------------------------------------------+
        |  Set EBIU0 Bank 4
        +--------------------------------------------------------------------*/
        lis     r10,EBIU0_BRCR4_VAL@h
        ori     r10,r10,EBIU0_BRCR4_VAL@l
        mtdcr   ebiu0_brcr4,r10
        lis     r10,EBIU0_BRCRH4_VAL@h
        ori     r10,r10,EBIU0_BRCRH4_VAL@l
        mtdcr   ebiu0_brcrh4,r10

        /*--------------------------------------------------------------------+