feature.c

linux内核源码

	LOCK(flags);
	if (value) {
		MACIO_BIC(KEYLARGO_FCR0, fcrs[cell][0]);
		MACIO_BIS(KEYLARGO_FCR1, fcrs[cell][1]);
		MACIO_BIS(KEYLARGO_FCR3, fcrs[cell][2]);
	} else {
		MACIO_BIC(KEYLARGO_FCR3, fcrs[cell][2]);
		MACIO_BIC(KEYLARGO_FCR1, fcrs[cell][1]);
		MACIO_BIS(KEYLARGO_FCR0, fcrs[cell][0]);
	}
	udelay(10);
	UNLOCK(flags);

	return 0;
}


#ifdef CONFIG_SMP
static long g5_reset_cpu(struct device_node *node, long param, long value)
{
	unsigned int reset_io = 0;
	unsigned long flags;
	struct macio_chip *macio;
	struct device_node *np;
	struct device_node *cpus;

	macio = &macio_chips[0];
	if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
		return -ENODEV;

	cpus = of_find_node_by_path("/cpus");
	if (cpus == NULL)
		return -ENODEV;
	for (np = cpus->child; np != NULL; np = np->sibling) {
		const u32 *num = of_get_property(np, "reg", NULL);
		const u32 *rst = of_get_property(np, "soft-reset", NULL);
		if (num == NULL || rst == NULL)
			continue;
		if (param == *num) {
			reset_io = *rst;
			break;
		}
	}
	of_node_put(cpus);
	if (np == NULL || reset_io == 0)
		return -ENODEV;

	LOCK(flags);
	MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
	(void)MACIO_IN8(reset_io);
	udelay(1);
	MACIO_OUT8(reset_io, 0);
	(void)MACIO_IN8(reset_io);
	UNLOCK(flags);

	return 0;
}
#endif /* CONFIG_SMP */

/*
 * This can be called from pmac_smp so isn't static
 *
 * This takes the second CPU off the bus on dual CPU machines
 * running UP
 */
void g5_phy_disable_cpu1(void)
{
	if (uninorth_maj == 3)
		UN_OUT(U3_API_PHY_CONFIG_1, 0);
}
#endif /* CONFIG_POWER4 */

#ifndef CONFIG_POWER4


#ifdef CONFIG_PM
static u32 save_gpio_levels[2];
static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT];
static u8 save_gpio_normal[KEYLARGO_GPIO_CNT];
static u32 save_unin_clock_ctl;

static void keylargo_shutdown(struct macio_chip *macio, int sleep_mode)
{
	u32 temp;

	if (sleep_mode) {
		mdelay(1);
		MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND);
		(void)MACIO_IN32(KEYLARGO_FCR0);
		mdelay(1);
	}

	MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
				KL0_SCC_CELL_ENABLE |
				KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
				KL0_IRDA_CLK19_ENABLE);

	MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
	MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);

	MACIO_BIC(KEYLARGO_FCR1,
		KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
		KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
		KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
		KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
		KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
		KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N |
		KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N |
		KL1_UIDE_ENABLE);

	MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
	MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE);

	temp = MACIO_IN32(KEYLARGO_FCR3);
	if (macio->rev >= 2) {
		temp |= KL3_SHUTDOWN_PLL2X;
		if (sleep_mode)
			temp |= KL3_SHUTDOWN_PLL_TOTAL;
	}

	temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
		KL3_SHUTDOWN_PLLKW35;
	if (sleep_mode)
		temp |= KL3_SHUTDOWN_PLLKW12;
	temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE
		| KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
	if (sleep_mode)
		temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE);
	MACIO_OUT32(KEYLARGO_FCR3, temp);

	/* Flush posted writes & wait a bit */
	(void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
}

static void pangea_shutdown(struct macio_chip *macio, int sleep_mode)
{
	u32 temp;

	MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
				KL0_SCC_CELL_ENABLE |
				KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);

	MACIO_BIC(KEYLARGO_FCR1,
		KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
		KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
		KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
		KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
		KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
		KL1_UIDE_ENABLE);
	if (pmac_mb.board_flags & PMAC_MB_MOBILE)
		MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);

	MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);

	temp = MACIO_IN32(KEYLARGO_FCR3);
	temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
		KL3_SHUTDOWN_PLLKW35;
	temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE
		| KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE);
	if (sleep_mode)
		temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE);
	MACIO_OUT32(KEYLARGO_FCR3, temp);

	/* Flush posted writes & wait a bit */
	(void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
}

static void intrepid_shutdown(struct macio_chip *macio, int sleep_mode)
{
	u32 temp;

	MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
		  KL0_SCC_CELL_ENABLE);

	MACIO_BIC(KEYLARGO_FCR1,
		KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
		KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
		KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
		KL1_EIDE0_ENABLE);
	if (pmac_mb.board_flags & PMAC_MB_MOBILE)
		MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);

	temp = MACIO_IN32(KEYLARGO_FCR3);
	temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE |
		  KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
	if (sleep_mode)
		temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE);
	MACIO_OUT32(KEYLARGO_FCR3, temp);

	/* Flush posted writes & wait a bit */
	(void)MACIO_IN32(KEYLARGO_FCR0);
	mdelay(10);
}


static int
core99_sleep(void)
{
	struct macio_chip *macio;
	int i;

	macio = &macio_chips[0];
	if (macio->type != macio_keylargo && macio->type != macio_pangea &&
	    macio->type != macio_intrepid)
		return -ENODEV;

	/* We power off the wireless slot in case it was not done
	 * by the driver. We don't power it on automatically however
	 */
	if (macio->flags & MACIO_FLAG_AIRPORT_ON)
		core99_airport_enable(macio->of_node, 0, 0);

	/* We power off the FW cable. Should be done by the driver... */
	if (macio->flags & MACIO_FLAG_FW_SUPPORTED) {
		core99_firewire_enable(NULL, 0, 0);
		core99_firewire_cable_power(NULL, 0, 0);
	}

	/* We make sure int. modem is off (in case driver lost it) */
	if (macio->type == macio_keylargo)
		core99_modem_enable(macio->of_node, 0, 0);
	else
		pangea_modem_enable(macio->of_node, 0, 0);

	/* We make sure the sound is off as well */
	core99_sound_chip_enable(macio->of_node, 0, 0);

	/*
	 * Save various bits of KeyLargo
	 */

	/* Save the state of the various GPIOs */
	save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0);
	save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1);
	for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
		save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i);
	for (i=0; i<KEYLARGO_GPIO_CNT; i++)
		save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i);

	/* Save the FCRs */
	if (macio->type == macio_keylargo)
		save_mbcr = MACIO_IN32(KEYLARGO_MBCR);
	save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0);
	save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1);
	save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2);
	save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3);
	save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4);
	if (macio->type == macio_pangea || macio->type == macio_intrepid)
		save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5);

	/* Save state & config of DBDMA channels */
	dbdma_save(macio, save_dbdma);

	/*
	 * Turn off as much as we can
	 */
	if (macio->type == macio_pangea)
		pangea_shutdown(macio, 1);
	else if (macio->type == macio_intrepid)
		intrepid_shutdown(macio, 1);
	else if (macio->type == macio_keylargo)
		keylargo_shutdown(macio, 1);

	/*
	 * Put the host bridge to sleep
	 */

	save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL);
	/* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it
	 * enabled !
	 */
	UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl &
	       ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/));
	udelay(100);
	UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
	UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP);
	mdelay(10);

	/*
	 * FIXME: A bit of black magic with OpenPIC (don't ask me why)
	 */
	if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
		MACIO_BIS(0x506e0, 0x00400000);
		MACIO_BIS(0x506e0, 0x80000000);
	}
	return 0;
}

static int
core99_wake_up(void)
{
	struct macio_chip *macio;
	int i;

	macio = &macio_chips[0];
	if (macio->type != macio_keylargo && macio->type != macio_pangea &&
	    macio->type != macio_intrepid)
		return -ENODEV;

	/*
	 * Wakeup the host bridge
	 */
	UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
	udelay(10);
	UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
	udelay(10);

	/*
	 * Restore KeyLargo
	 */

	if (macio->type == macio_keylargo) {
		MACIO_OUT32(KEYLARGO_MBCR, save_mbcr);
		(void)MACIO_IN32(KEYLARGO_MBCR); udelay(10);
	}
	MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]);
	(void)MACIO_IN32(KEYLARGO_FCR0); udelay(10);
	MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]);
	(void)MACIO_IN32(KEYLARGO_FCR1); udelay(10);
	MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]);
	(void)MACIO_IN32(KEYLARGO_FCR2); udelay(10);
	MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]);
	(void)MACIO_IN32(KEYLARGO_FCR3); udelay(10);
	MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]);
	(void)MACIO_IN32(KEYLARGO_FCR4); udelay(10);
	if (macio->type == macio_pangea || macio->type == macio_intrepid) {
		MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]);
		(void)MACIO_IN32(KEYLARGO_FCR5); udelay(10);
	}

	dbdma_restore(macio, save_dbdma);

	MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]);
	MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]);
	for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
		MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]);
	for (i=0; i<KEYLARGO_GPIO_CNT; i++)
		MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]);

	/* FIXME more black magic with OpenPIC ... */
	if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
		MACIO_BIC(0x506e0, 0x00400000);
		MACIO_BIC(0x506e0, 0x80000000);
	}

	UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
	udelay(100);

	return 0;
}

#endif /* CONFIG_PM */

static long
core99_sleep_state(struct device_node *node, long param, long value)
{
	/* Param == 1 means to enter the "fake sleep" mode that is
	 * used for CPU speed switch
	 */
	if (param == 1) {
		if (value == 1) {
			UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
			UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2);
		} else {
			UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
			udelay(10);
			UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
			udelay(10);
		}
		return 0;
	}
	if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
		return -EPERM;

#ifdef CONFIG_PM
	if (value == 1)
		return core99_sleep();
	else if (value == 0)
		return core99_wake_up();

#endif /* CONFIG_PM */
	return 0;
}

#endif /* CONFIG_POWER4 */

static long
generic_dev_can_wake(struct device_node *node, long param, long value)
{
	/* Todo: eventually check we are really dealing with on-board
	 * video device ...
	 */

	if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP)
		pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP;
	return 0;
}

static long generic_get_mb_info(struct device_node *node, long param, long value)
{
	switch(param) {
		case PMAC_MB_INFO_MODEL:
			return pmac_mb.model_id;
		case PMAC_MB_INFO_FLAGS:
			return pmac_mb.board_flags;
		case PMAC_MB_INFO_NAME:
			/* hack hack hack... but should work */
			*((const char **)value) = pmac_mb.model_name;
			return 0;
	}
	return -EINVAL;
}


/*
 * Table definitions
 */

/* Used on any machine
 */
static struct feature_table_entry any_features[] = {
	{ PMAC_FTR_GET_MB_INFO,		generic_get_mb_info },
	{ PMAC_FTR_DEVICE_CAN_WAKE,	generic_dev_can_wake },
	{ 0, NULL }
};

#ifndef CONFIG_POWER4

/* OHare based motherboards. Currently, we only use these on the
 * 2400,3400 and 3500 series powerbooks. Some older desktops seem
 * to have issues with turning on/off those asic cells
 */
static struct feature_table_entry ohare_features[] = {
	{ PMAC_FTR_SCC_ENABLE,		ohare_htw_scc_enable },
	{ PMAC_FTR_SWIM3_ENABLE,	ohare_floppy_enable },
	{ PMAC_FTR_MESH_ENABLE,		ohare_mesh_enable },
	{ PMAC_FTR_IDE_ENABLE,		ohare_ide_enable},
	{ PMAC_FTR_IDE_RESET,		ohare_ide_reset},
	{ PMAC_FTR_SLEEP_STATE,		ohare_sleep_state },
	{ 0, NULL }
};

/* Heathrow desktop machines (Beige G3).
 * Separated as some features couldn't be properly tested
 * and the serial port control bits appear to confuse it.
 */
static struct feature_table_entry heathrow_desktop_features[] = {
	{ PMAC_FTR_SWIM3_ENABLE,	heathrow_floppy_enable },
	{ PMAC_FTR_MESH_ENABLE,		heathrow_mesh_enable },
	{ PMAC_FTR_IDE_ENABLE,		heathrow_ide_enable },
	{ PMAC_FTR_IDE_RESET,		heathrow_ide_reset },
	{ PMAC_FTR_BMAC_ENABLE,		heathrow_bmac_enable },
	{ 0, NULL }
};

/* Heathrow based laptop, that is the Wallstreet and mainstreet
 * powerbooks.
 */
static struct feature_table_entry heathrow_laptop_features[] = {
	{ PMAC_FTR_SCC_ENABLE,		ohare_htw_scc_enable },
	{ PMAC_FTR_MODEM_ENABLE,	heathrow_modem_enable },
	{ PMAC_FTR_SWIM3_ENABLE,	heathrow_floppy_enable },
	{ PMAC_FTR_MESH_ENABLE,		heathrow_mesh_enable },
	{ PMAC_FTR_IDE_ENABLE,		heathrow_ide_enable },
	{ PMAC_FTR_IDE_RESET,		heathrow_ide_reset },
	{ PMAC_FTR_BMAC_ENABLE,		heathrow_bmac_enable },
	{ PMAC_FTR_SOUND_CHIP_ENABLE,	heathrow_sound_enable },
	{ PMAC_FTR_SLEEP_STATE,		heathrow_sleep_state },
	{ 0, NULL }
};

/* Paddington based machines
 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
 */
static struct feature_table_entry paddington_features[] = {
	{ PMAC_FTR_SCC_ENABLE,		ohare_htw_scc_enable },
	{ PMAC_FTR_MODEM_ENABLE,	heathrow_modem_enable },
	{ PMAC_FTR_SWIM3_ENABLE,	heathrow_floppy_enable },
	{ PMAC_FTR_MESH_ENABLE,		heathrow_mesh_enable },
	{ PMAC_FTR_IDE_ENABLE,		heathrow_ide_enable },
	{ PMAC_FTR_IDE_RESET,		heathrow_ide_reset },
	{ PMAC_FTR_BMAC_ENABLE,		heathrow_bmac_enable },
	{ PMAC_FTR_SOUND_CHIP_ENABLE,	heathrow_sound_enable },
	{ PMAC_FTR_SLEEP_STATE,		heathrow_sleep_state },
	{ 0, NULL }
};

/* Core99 & MacRISC 2 machines (all machines released since the
 * iBook (included), that is all AGP machines, except pangea
 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
 * used on iBook2 & iMac "flow power".
 */
static struct feature_table_entry core99_features[] = {