setup.c

linux内核源码

	/* TMR */
	for (i = 0; i < TX4938_NR_TMR; i++)
		txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);

	/* enable DMA */
	TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
	TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);

	/* PIO */
	tx4938_pioptr->maskcpu = 0;
	tx4938_pioptr->maskext = 0;

	/* TX4938 internal registers */
	if (request_resource(&iomem_resource, &tx4938_reg_resource))
		printk("request resource for internal registers failed\n");
}

#ifdef CONFIG_PCI
static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
{
	unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
	unsigned long g2pstatus = pcicptr->g2pstatus;
	unsigned long pcicstatus = pcicptr->pcicstatus;
	static struct {
		unsigned long flag;
		const char *str;
	} pcistat_tbl[] = {
		{ PCI_STATUS_DETECTED_PARITY,	"DetectedParityError" },
		{ PCI_STATUS_SIG_SYSTEM_ERROR,	"SignaledSystemError" },
		{ PCI_STATUS_REC_MASTER_ABORT,	"ReceivedMasterAbort" },
		{ PCI_STATUS_REC_TARGET_ABORT,	"ReceivedTargetAbort" },
		{ PCI_STATUS_SIG_TARGET_ABORT,	"SignaledTargetAbort" },
		{ PCI_STATUS_PARITY,	"MasterParityError" },
	}, g2pstat_tbl[] = {
		{ TX4938_PCIC_G2PSTATUS_TTOE,	"TIOE" },
		{ TX4938_PCIC_G2PSTATUS_RTOE,	"RTOE" },
	}, pcicstat_tbl[] = {
		{ TX4938_PCIC_PCICSTATUS_PME,	"PME" },
		{ TX4938_PCIC_PCICSTATUS_TLB,	"TLB" },
		{ TX4938_PCIC_PCICSTATUS_NIB,	"NIB" },
		{ TX4938_PCIC_PCICSTATUS_ZIB,	"ZIB" },
		{ TX4938_PCIC_PCICSTATUS_PERR,	"PERR" },
		{ TX4938_PCIC_PCICSTATUS_SERR,	"SERR" },
		{ TX4938_PCIC_PCICSTATUS_GBE,	"GBE" },
		{ TX4938_PCIC_PCICSTATUS_IWB,	"IWB" },
	};
	int i;

	printk("pcistat:%04x(", pcistatus);
	for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
		if (pcistatus & pcistat_tbl[i].flag)
			printk("%s ", pcistat_tbl[i].str);
	printk("), g2pstatus:%08lx(", g2pstatus);
	for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
		if (g2pstatus & g2pstat_tbl[i].flag)
			printk("%s ", g2pstat_tbl[i].str);
	printk("), pcicstatus:%08lx(", pcicstatus);
	for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
		if (pcicstatus & pcicstat_tbl[i].flag)
			printk("%s ", pcicstat_tbl[i].str);
	printk(")\n");
}

void tx4938_report_pcic_status(void)
{
	int i;
	struct tx4938_pcic_reg *pcicptr;
	for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
		tx4938_report_pcic_status1(pcicptr);
}

#endif /* CONFIG_PCI */

void __init plat_time_init(void)
{
	mips_hpt_frequency = txx9_cpu_clock / 2;
	if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS)
		txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
				     TXX9_IRQ_BASE + TX4938_IR_TMR(0),
				     txx9_gbus_clock / 2);
}

void __init toshiba_rbtx4938_setup(void)
{
	unsigned long long pcfg;
	char *argptr;

	iomem_resource.end = 0xffffffff;	/* 4GB */

	if (txx9_master_clock == 0)
		txx9_master_clock = 25000000; /* 25MHz */
	tx4938_board_setup();
	/* setup serial stuff */
	TX4938_WR(0xff1ff314, 0x00000000);	/* h/w flow control off */
	TX4938_WR(0xff1ff414, 0x00000000);	/* h/w flow control off */

#ifndef CONFIG_PCI
	set_io_port_base(RBTX4938_ETHER_BASE);
#endif

#ifdef CONFIG_SERIAL_TXX9
	{
		extern int early_serial_txx9_setup(struct uart_port *port);
		int i;
		struct uart_port req;
		for(i = 0; i < 2; i++) {
			memset(&req, 0, sizeof(req));
			req.line = i;
			req.iotype = UPIO_MEM;
			req.membase = (char *)(0xff1ff300 + i * 0x100);
			req.mapbase = 0xff1ff300 + i * 0x100;
			req.irq = RBTX4938_IRQ_IRC_SIO(i);
			req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
			req.uartclk = 50000000;
			early_serial_txx9_setup(&req);
		}
	}
#ifdef CONFIG_SERIAL_TXX9_CONSOLE
        argptr = prom_getcmdline();
        if (strstr(argptr, "console=") == NULL) {
                strcat(argptr, " console=ttyS0,38400");
        }
#endif
#endif

#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
	printk("PIOSEL: disabling both ata and nand selection\n");
	local_irq_disable();
	tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
#endif

#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
	printk("PIOSEL: enabling nand selection\n");
	tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
	tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
#endif

#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
	printk("PIOSEL: enabling ata selection\n");
	tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
	tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
#endif

#ifdef CONFIG_IP_PNP
	argptr = prom_getcmdline();
	if (strstr(argptr, "ip=") == NULL) {
		strcat(argptr, " ip=any");
	}
#endif


#ifdef CONFIG_FB
	{
		conswitchp = &dummy_con;
	}
#endif

	rbtx4938_spi_setup();
	pcfg = tx4938_ccfgptr->pcfg;	/* updated */
	/* fixup piosel */
	if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
	    TX4938_PCFG_ATA_SEL) {
		*rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
	}
	else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
	    TX4938_PCFG_NDF_SEL) {
		*rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
	}
	else {
		*rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
	}

	rbtx4938_fpga_resource.name = "FPGA Registers";
	rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
	rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
	rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
	if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
		printk("request resource for fpga failed\n");

	/* disable all OnBoard I/O interrupts */
	*rbtx4938_imask_ptr = 0;

	_machine_restart = rbtx4938_machine_restart;
	_machine_halt = rbtx4938_machine_halt;
	pm_power_off = rbtx4938_machine_power_off;

	*rbtx4938_led_ptr = 0xff;
	printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
	printk(" DIPSW:%02x,%02x\n",
	       *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
}

static int __init rbtx4938_ne_init(void)
{
	struct resource res[] = {
		{
			.start	= RBTX4938_RTL_8019_BASE,
			.end	= RBTX4938_RTL_8019_BASE + 0x20 - 1,
			.flags	= IORESOURCE_IO,
		}, {
			.start	= RBTX4938_RTL_8019_IRQ,
			.flags	= IORESOURCE_IRQ,
		}
	};
	struct platform_device *dev =
		platform_device_register_simple("ne", -1,
						res, ARRAY_SIZE(res));
	return IS_ERR(dev) ? PTR_ERR(dev) : 0;
}
device_initcall(rbtx4938_ne_init);

/* GPIO support */

static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);

static void rbtx4938_spi_gpio_set(unsigned gpio, int value)
{
	u8 val;
	unsigned long flags;
	gpio -= 16;
	spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
	val = *rbtx4938_spics_ptr;
	if (value)
		val |= 1 << gpio;
	else
		val &= ~(1 << gpio);
	*rbtx4938_spics_ptr = val;
	mmiowb();
	spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
}

static int rbtx4938_spi_gpio_dir_out(unsigned gpio, int value)
{
	rbtx4938_spi_gpio_set(gpio, value);
	return 0;
}

static DEFINE_SPINLOCK(tx4938_gpio_lock);

static int tx4938_gpio_get(unsigned gpio)
{
	return tx4938_pioptr->din & (1 << gpio);
}

static void tx4938_gpio_set_raw(unsigned gpio, int value)
{
	u32 val;
	val = tx4938_pioptr->dout;
	if (value)
		val |= 1 << gpio;
	else
		val &= ~(1 << gpio);
	tx4938_pioptr->dout = val;
}

static void tx4938_gpio_set(unsigned gpio, int value)
{
	unsigned long flags;
	spin_lock_irqsave(&tx4938_gpio_lock, flags);
	tx4938_gpio_set_raw(gpio, value);
	mmiowb();
	spin_unlock_irqrestore(&tx4938_gpio_lock, flags);
}

static int tx4938_gpio_dir_in(unsigned gpio)
{
	spin_lock_irq(&tx4938_gpio_lock);
	tx4938_pioptr->dir &= ~(1 << gpio);
	mmiowb();
	spin_unlock_irq(&tx4938_gpio_lock);
	return 0;
}

static int tx4938_gpio_dir_out(unsigned int gpio, int value)
{
	spin_lock_irq(&tx4938_gpio_lock);
	tx4938_gpio_set_raw(gpio, value);
	tx4938_pioptr->dir |= 1 << gpio;
	mmiowb();
	spin_unlock_irq(&tx4938_gpio_lock);
	return 0;
}

int gpio_direction_input(unsigned gpio)
{
	if (gpio < 16)
		return tx4938_gpio_dir_in(gpio);
	return -EINVAL;
}

int gpio_direction_output(unsigned gpio, int value)
{
	if (gpio < 16)
		return tx4938_gpio_dir_out(gpio, value);
	if (gpio < 16 + 3)
		return rbtx4938_spi_gpio_dir_out(gpio, value);
	return -EINVAL;
}

int gpio_get_value(unsigned gpio)
{
	if (gpio < 16)
		return tx4938_gpio_get(gpio);
	return 0;
}

void gpio_set_value(unsigned gpio, int value)
{
	if (gpio < 16)
		tx4938_gpio_set(gpio, value);
	else
		rbtx4938_spi_gpio_set(gpio, value);
}

/* SPI support */

static void __init txx9_spi_init(unsigned long base, int irq)
{
	struct resource res[] = {
		{
			.start	= base,
			.end	= base + 0x20 - 1,
			.flags	= IORESOURCE_MEM,
			.parent	= &tx4938_reg_resource,
		}, {
			.start	= irq,
			.flags	= IORESOURCE_IRQ,
		},
	};
	platform_device_register_simple("spi_txx9", 0,
					res, ARRAY_SIZE(res));
}

static int __init rbtx4938_spi_init(void)
{
	struct spi_board_info srtc_info = {
		.modalias = "rtc-rs5c348",
		.max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
		.bus_num = 0,
		.chip_select = 16 + SRTC_CS,
		/* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS  */
		.mode = SPI_MODE_1 | SPI_CS_HIGH,
	};
	spi_register_board_info(&srtc_info, 1);
	spi_eeprom_register(SEEPROM1_CS);
	spi_eeprom_register(16 + SEEPROM2_CS);
	spi_eeprom_register(16 + SEEPROM3_CS);
	txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
	return 0;
}
arch_initcall(rbtx4938_spi_init);

/* Minimum CLK support */

struct clk *clk_get(struct device *dev, const char *id)
{
	if (!strcmp(id, "spi-baseclk"))
		return (struct clk *)(txx9_gbus_clock / 2 / 4);
	return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);

int clk_enable(struct clk *clk)
{
	return 0;
}
EXPORT_SYMBOL(clk_enable);

void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);

unsigned long clk_get_rate(struct clk *clk)
{
	return (unsigned long)clk;
}
EXPORT_SYMBOL(clk_get_rate);

void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);