reg_16.tan.qmsg

8位十进制乘法器

{ "Info" "ITDB_FULL_TCO_RESULT" "r16_clk r16_out\[0\] reg16\[0\] 11.500 ns register " "Info: tco from clock \"r16_clk\" to destination pin \"r16_out\[0\]\" through register \"reg16\[0\]\" is 11.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "r16_clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"r16_clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r16_clk 1 CLK PIN_55 22 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 22; CLK Node = 'r16_clk'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "" { r16_clk } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns reg16\[0\] 2 REG LC1_D35 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_D35; Fanout = 1; REG Node = 'reg16\[0\]'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "0.400 ns" { r16_clk reg16[0] } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk reg16[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out reg16[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.600 ns + Longest register pin " "Info: + Longest register to pin delay is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg16\[0\] 1 REG LC1_D35 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_D35; Fanout = 1; REG Node = 'reg16\[0\]'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "" { reg16[0] } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(6.300 ns) 8.600 ns r16_out\[0\] 2 PIN PIN_92 0 " "Info: 2: + IC(2.300 ns) + CELL(6.300 ns) = 8.600 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'r16_out\[0\]'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "8.600 ns" { reg16[0] r16_out[0] } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 73.26 % " "Info: Total cell delay = 6.300 ns ( 73.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 26.74 % " "Info: Total interconnect delay = 2.300 ns ( 26.74 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "8.600 ns" { reg16[0] r16_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { reg16[0] r16_out[0] } { 0.000ns 2.300ns } { 0.000ns 6.300ns } } }  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk reg16[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out reg16[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "8.600 ns" { reg16[0] r16_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { reg16[0] r16_out[0] } { 0.000ns 2.300ns } { 0.000ns 6.300ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "reg16\[7\] r16_in\[0\] r16_clk 0.700 ns register " "Info: th for register \"reg16\[7\]\" (data pin = \"r16_in\[0\]\", clock pin = \"r16_clk\") is 0.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "r16_clk destination 2.400 ns + Longest register " "Info: + Longest clock path from clock \"r16_clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r16_clk 1 CLK PIN_55 22 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 22; CLK Node = 'r16_clk'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "" { r16_clk } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns reg16\[7\] 2 REG LC3_D35 2 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_D35; Fanout = 2; REG Node = 'reg16\[7\]'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "0.400 ns" { r16_clk reg16[7] } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk reg16[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out reg16[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r16_in\[0\] 1 PIN PIN_56 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_56; Fanout = 1; PIN Node = 'r16_in\[0\]'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "" { r16_in[0] } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.800 ns) 3.000 ns reg16\[7\] 2 REG LC3_D35 2 " "Info: 2: + IC(0.200 ns) + CELL(0.800 ns) = 3.000 ns; Loc. = LC3_D35; Fanout = 2; REG Node = 'reg16\[7\]'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "1.000 ns" { r16_in[0] reg16[7] } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 93.33 % " "Info: Total cell delay = 2.800 ns ( 93.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 6.67 % " "Info: Total interconnect delay = 0.200 ns ( 6.67 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "3.000 ns" { r16_in[0] reg16[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { r16_in[0] r16_in[0]~out reg16[7] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 0.800ns } } }  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk reg16[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out reg16[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "3.000 ns" { r16_in[0] reg16[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { r16_in[0] r16_in[0]~out reg16[7] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 0.800ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 19 15:44:21 2012 " "Info: Processing ended: Wed Dec 19 15:44:21 2012" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}