⭐ 欢迎来到虫虫下载站！ | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站
📤 上传资源

📄 reg_16.tan.qmsg

📁 8位十进制乘法器
💻 QMSG
📖 第 1 页 / 共 3 页
字号:
🔍
123 
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "r16_clk " "Info: Assuming node \"r16_clk\" is an undefined clock" {  } { { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "r16_clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "r16_clk register lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] register cout~reg0 149.25 MHz 6.7 ns Internal " "Info: Clock \"r16_clk\" has Internal fmax of 149.25 MHz between source register \"lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]\" and destination register \"cout~reg0\" (period= 6.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns + Longest register register " "Info: + Longest register to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] 1 REG LC6_C35 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_C35; Fanout = 5; REG Node = 'lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 2.000 ns reduce_nor~18 2 COMB LC1_C35 17 " "Info: 2: + IC(0.300 ns) + CELL(1.700 ns) = 2.000 ns; Loc. = LC1_C35; Fanout = 17; COMB Node = 'reduce_nor~18'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.000 ns" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] reduce_nor~18 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.400 ns) 4.300 ns cout~2 3 COMB LC1_C36 1 " "Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 4.300 ns; Loc. = LC1_C36; Fanout = 1; COMB Node = 'cout~2'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.300 ns" { reduce_nor~18 cout~2 } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 5.600 ns cout~reg0 4 REG LC2_C36 1 " "Info: 4: + IC(0.300 ns) + CELL(1.000 ns) = 5.600 ns; Loc. = LC2_C36; Fanout = 1; REG Node = 'cout~reg0'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "1.300 ns" { cout~2 cout~reg0 } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.100 ns 73.21 % " "Info: Total cell delay = 4.100 ns ( 73.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns 26.79 % " "Info: Total interconnect delay = 1.500 ns ( 26.79 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "5.600 ns" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] reduce_nor~18 cout~2 cout~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.600 ns" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] reduce_nor~18 cout~2 cout~reg0 } { 0.000ns 0.300ns 0.900ns 0.300ns } { 0.000ns 1.700ns 1.400ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "r16_clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"r16_clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r16_clk 1 CLK PIN_55 22 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 22; CLK Node = 'r16_clk'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "" { r16_clk } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns cout~reg0 2 REG LC2_C36 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_C36; Fanout = 1; REG Node = 'cout~reg0'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "0.400 ns" { r16_clk cout~reg0 } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk cout~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out cout~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "r16_clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"r16_clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r16_clk 1 CLK PIN_55 22 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 22; CLK Node = 'r16_clk'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "" { r16_clk } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] 2 REG LC6_C35 5 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_C35; Fanout = 5; REG Node = 'lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "0.400 ns" { r16_clk lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk cout~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out cout~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 17 -1 0 } }  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "5.600 ns" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] reduce_nor~18 cout~2 cout~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.600 ns" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] reduce_nor~18 cout~2 cout~reg0 } { 0.000ns 0.300ns 0.900ns 0.300ns } { 0.000ns 1.700ns 1.400ns 1.000ns } } } { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk cout~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out cout~reg0 } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "reg16\[14\] r16_in\[7\] r16_clk 6.400 ns register " "Info: tsu for register \"reg16\[14\]\" (data pin = \"r16_in\[7\]\", clock pin = \"r16_clk\") is 6.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.200 ns + Longest pin register " "Info: + Longest pin to register delay is 8.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns r16_in\[7\] 1 PIN PIN_97 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_97; Fanout = 1; PIN Node = 'r16_in\[7\]'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "" { r16_in[7] } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.800 ns) 8.200 ns reg16\[14\] 2 REG LC8_C32 1 " "Info: 2: + IC(2.500 ns) + CELL(0.800 ns) = 8.200 ns; Loc. = LC8_C32; Fanout = 1; REG Node = 'reg16\[14\]'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "3.300 ns" { r16_in[7] reg16[14] } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns 69.51 % " "Info: Total cell delay = 5.700 ns ( 69.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 30.49 % " "Info: Total interconnect delay = 2.500 ns ( 30.49 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "8.200 ns" { r16_in[7] reg16[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.200 ns" { r16_in[7] r16_in[7]~out reg16[14] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 4.900ns 0.800ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "r16_clk destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"r16_clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns r16_clk 1 CLK PIN_55 22 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 22; CLK Node = 'r16_clk'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "" { r16_clk } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns reg16\[14\] 2 REG LC8_C32 1 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC8_C32; Fanout = 1; REG Node = 'reg16\[14\]'" {  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "0.400 ns" { r16_clk reg16[14] } "NODE_NAME" } "" } } { "reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk reg16[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out reg16[14] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "8.200 ns" { r16_in[7] reg16[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.200 ns" { r16_in[7] r16_in[7]~out reg16[14] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 4.900ns 0.800ns } } } { "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" "" { Report "F:/8位十进制乘法器/reg_16/db/reg_16_cmp.qrpt" Compiler "reg_16" "UNKNOWN" "V1" "F:/8位十进制乘法器/reg_16/db/reg_16.quartus_db" { Floorplan "F:/8位十进制乘法器/reg_16/" "" "2.400 ns" { r16_clk reg16[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { r16_clk r16_clk~out reg16[14] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
123

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -