📄 reg_16.map.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
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-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L8Q is cout~reg0
--operation mode is normal
A1L8Q_lut_out = VCC;
A1L8Q = DFFEA(A1L8Q_lut_out, r16_clk, !A1L3, , A1L4, , );
--A1L5Q is cout~3
--operation mode is normal
A1L5Q = A1L8Q;
--reg16[0] is reg16[0]
--operation mode is normal
reg16[0]_lut_out = reg16[1];
reg16[0] = DFFEA(reg16[0]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L44Q is reg16[0]~16
--operation mode is normal
A1L44Q = reg16[0];
--reg16[1] is reg16[1]
--operation mode is normal
reg16[1]_lut_out = reg16[2];
reg16[1] = DFFEA(reg16[1]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L64Q is reg16[1]~17
--operation mode is normal
A1L64Q = reg16[1];
--reg16[2] is reg16[2]
--operation mode is normal
reg16[2]_lut_out = reg16[3];
reg16[2] = DFFEA(reg16[2]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L84Q is reg16[2]~18
--operation mode is normal
A1L84Q = reg16[2];
--reg16[3] is reg16[3]
--operation mode is normal
reg16[3]_lut_out = reg16[4];
reg16[3] = DFFEA(reg16[3]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L05Q is reg16[3]~19
--operation mode is normal
A1L05Q = reg16[3];
--reg16[4] is reg16[4]
--operation mode is normal
reg16[4]_lut_out = reg16[5];
reg16[4] = DFFEA(reg16[4]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L25Q is reg16[4]~20
--operation mode is normal
A1L25Q = reg16[4];
--reg16[5] is reg16[5]
--operation mode is normal
reg16[5]_lut_out = reg16[6];
reg16[5] = DFFEA(reg16[5]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L45Q is reg16[5]~21
--operation mode is normal
A1L45Q = reg16[5];
--reg16[6] is reg16[6]
--operation mode is normal
reg16[6]_lut_out = reg16[7];
reg16[6] = DFFEA(reg16[6]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L65Q is reg16[6]~22
--operation mode is normal
A1L65Q = reg16[6];
--reg16[7] is reg16[7]
--operation mode is normal
reg16[7]_lut_out = r16_in[0];
reg16[7] = DFFEA(reg16[7]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L85Q is reg16[7]~23
--operation mode is normal
A1L85Q = reg16[7];
--reg16[8] is reg16[8]
--operation mode is normal
reg16[8]_lut_out = r16_in[1];
reg16[8] = DFFEA(reg16[8]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L06Q is reg16[8]~24
--operation mode is normal
A1L06Q = reg16[8];
--reg16[9] is reg16[9]
--operation mode is normal
reg16[9]_lut_out = r16_in[2];
reg16[9] = DFFEA(reg16[9]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L26Q is reg16[9]~25
--operation mode is normal
A1L26Q = reg16[9];
--reg16[10] is reg16[10]
--operation mode is normal
reg16[10]_lut_out = r16_in[3];
reg16[10] = DFFEA(reg16[10]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L46Q is reg16[10]~26
--operation mode is normal
A1L46Q = reg16[10];
--reg16[11] is reg16[11]
--operation mode is normal
reg16[11]_lut_out = r16_in[4];
reg16[11] = DFFEA(reg16[11]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L66Q is reg16[11]~27
--operation mode is normal
A1L66Q = reg16[11];
--reg16[12] is reg16[12]
--operation mode is normal
reg16[12]_lut_out = r16_in[5];
reg16[12] = DFFEA(reg16[12]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L86Q is reg16[12]~28
--operation mode is normal
A1L86Q = reg16[12];
--reg16[13] is reg16[13]
--operation mode is normal
reg16[13]_lut_out = r16_in[6];
reg16[13] = DFFEA(reg16[13]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L07Q is reg16[13]~29
--operation mode is normal
A1L07Q = reg16[13];
--reg16[14] is reg16[14]
--operation mode is normal
reg16[14]_lut_out = r16_in[7];
reg16[14] = DFFEA(reg16[14]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L27Q is reg16[14]~30
--operation mode is normal
A1L27Q = reg16[14];
--reg16[15] is reg16[15]
--operation mode is normal
reg16[15]_lut_out = r16_in[8];
reg16[15] = DFFEA(reg16[15]_lut_out, r16_clk, !A1L3, , A1L83, , );
--A1L47Q is reg16[15]~31
--operation mode is normal
A1L47Q = reg16[15];
--A1L3 is cout~0
--operation mode is normal
A1L3 = clr # r16_clr;
--A1L6 is cout~4
--operation mode is normal
A1L6 = clr # r16_clr;
--C1_q[2] is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr
C1_q[2]_lut_out = (C1_q[2] $ (C1L9 & C1L5)) & VCC;
C1_q[2] = DFFEA(C1_q[2]_lut_out, r16_clk, !r16_clr, , , , );
--C1L71Q is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~0
--operation mode is clrb_cntr
C1L71Q = C1_q[2];
--C1L7 is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr
C1L7 = CARRY(C1_q[2] & (C1L5));
--C1_q[1] is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr
C1_q[1]_lut_out = (C1_q[1] $ (C1L9 & C1L3)) & VCC;
C1_q[1] = DFFEA(C1_q[1]_lut_out, r16_clk, !r16_clr, , , , );
--C1L51Q is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is clrb_cntr
C1L51Q = C1_q[1];
--C1L5 is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr
C1L5 = CARRY(C1_q[1] & (C1L3));
--C1_q[0] is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr
C1_q[0]_lut_out = (C1L9 $ C1_q[0]) & VCC;
C1_q[0] = DFFEA(C1_q[0]_lut_out, r16_clk, !r16_clr, , , , );
--C1L31Q is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~2
--operation mode is clrb_cntr
C1L31Q = C1_q[0];
--C1L3 is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr
C1L3 = CARRY(C1_q[0]);
--C1_q[3] is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr
C1_q[3]_lut_out = (C1_q[3] $ (C1L9 & C1L7)) & VCC;
C1_q[3] = DFFEA(C1_q[3]_lut_out, r16_clk, !r16_clr, , , , );
--C1L91Q is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is clrb_cntr
C1L91Q = C1_q[3];
--A1L83 is reduce_nor~18
--operation mode is normal
A1L83 = C1_q[2] # C1_q[1] # C1_q[0] # !C1_q[3];
--A1L04 is reduce_nor~20
--operation mode is normal
A1L04 = C1_q[2] # C1_q[1] # C1_q[0] # !C1_q[3];
--A1L93 is reduce_nor~19
--operation mode is normal
A1L93 = C1_q[1] # C1_q[0];
--A1L14 is reduce_nor~21
--operation mode is normal
A1L14 = C1_q[1] # C1_q[0];
--C1L9 is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~0
--operation mode is normal
C1L9 = !clr & (C1_q[2] # A1L93 # !C1_q[3]);
--C1L01 is lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~54
--operation mode is normal
C1L01 = !clr & (C1_q[2] # A1L93 # !C1_q[3]);
--A1L4 is cout~2
--operation mode is normal
A1L4 = !A1L83;
--A1L7 is cout~5
--operation mode is normal
A1L7 = !A1L83;
--r16_clk is r16_clk
--operation mode is input
r16_clk = INPUT();
--clr is clr
--operation mode is input
clr = INPUT();
--r16_clr is r16_clr
--operation mode is input
r16_clr = INPUT();
--r16_in[0] is r16_in[0]
--operation mode is input
r16_in[0] = INPUT();
--r16_in[1] is r16_in[1]
--operation mode is input
r16_in[1] = INPUT();
--r16_in[2] is r16_in[2]
--operation mode is input
r16_in[2] = INPUT();
--r16_in[3] is r16_in[3]
--operation mode is input
r16_in[3] = INPUT();
--r16_in[4] is r16_in[4]
--operation mode is input
r16_in[4] = INPUT();
--r16_in[5] is r16_in[5]
--operation mode is input
r16_in[5] = INPUT();
--r16_in[6] is r16_in[6]
--operation mode is input
r16_in[6] = INPUT();
--r16_in[7] is r16_in[7]
--operation mode is input
r16_in[7] = INPUT();
--r16_in[8] is r16_in[8]
--operation mode is input
r16_in[8] = INPUT();
--cout is cout
--operation mode is output
cout = OUTPUT(A1L8Q);
--r16_out[0] is r16_out[0]
--operation mode is output
r16_out[0] = OUTPUT(reg16[0]);
--r16_out[1] is r16_out[1]
--operation mode is output
r16_out[1] = OUTPUT(reg16[1]);
--r16_out[2] is r16_out[2]
--operation mode is output
r16_out[2] = OUTPUT(reg16[2]);
--r16_out[3] is r16_out[3]
--operation mode is output
r16_out[3] = OUTPUT(reg16[3]);
--r16_out[4] is r16_out[4]
--operation mode is output
r16_out[4] = OUTPUT(reg16[4]);
--r16_out[5] is r16_out[5]
--operation mode is output
r16_out[5] = OUTPUT(reg16[5]);
--r16_out[6] is r16_out[6]
--operation mode is output
r16_out[6] = OUTPUT(reg16[6]);
--r16_out[7] is r16_out[7]
--operation mode is output
r16_out[7] = OUTPUT(reg16[7]);
--r16_out[8] is r16_out[8]
--operation mode is output
r16_out[8] = OUTPUT(reg16[8]);
--r16_out[9] is r16_out[9]
--operation mode is output
r16_out[9] = OUTPUT(reg16[9]);
--r16_out[10] is r16_out[10]
--operation mode is output
r16_out[10] = OUTPUT(reg16[10]);
--r16_out[11] is r16_out[11]
--operation mode is output
r16_out[11] = OUTPUT(reg16[11]);
--r16_out[12] is r16_out[12]
--operation mode is output
r16_out[12] = OUTPUT(reg16[12]);
--r16_out[13] is r16_out[13]
--operation mode is output
r16_out[13] = OUTPUT(reg16[13]);
--r16_out[14] is r16_out[14]
--operation mode is output
r16_out[14] = OUTPUT(reg16[14]);
--r16_out[15] is r16_out[15]
--operation mode is output
r16_out[15] = OUTPUT(reg16[15]);
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