reg_16.map.rpt

8位十进制乘法器

; alt_counter_stratix.inc          ; yes             ; Other           ; c:/altera/quartus50/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal50.inc                    ; yes             ; Other           ; c:/altera/quartus50/libraries/megafunctions/aglobal50.inc           ;
; alt_counter_f10ke.tdf            ; yes             ; Megafunction    ; c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf   ;
; flex10ke_lcell.inc               ; yes             ; Other           ; c:/altera/quartus50/libraries/megafunctions/flex10ke_lcell.inc      ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 26      ;
; Total combinational functions     ; 10      ;
;     -- Total 4-input functions    ; 2       ;
;     -- Total 3-input functions    ; 0       ;
;     -- Total 2-input functions    ; 2       ;
;     -- Total 1-input functions    ; 5       ;
;     -- Total 0-input functions    ; 1       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 21      ;
; Total logic cells in carry chains ; 4       ;
; I/O pins                          ; 29      ;
; Maximum fan-out node              ; r16_clk ;
; Maximum fan-out                   ; 21      ;
; Total fan-out                     ; 112     ;
; Average fan-out                   ; 2.04    ;
+-----------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                           ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------+
; Compilation Hierarchy Node             ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                        ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------+
; |reg_16                                ; 26 (21)     ; 21           ; 0           ; 29   ; 5 (4)        ; 16 (16)           ; 5 (1)            ; 4 (0)           ; |reg_16                                                    ;
;    |lpm_counter:i_rtl_0|               ; 5 (0)       ; 4            ; 0           ; 0    ; 1 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |reg_16|lpm_counter:i_rtl_0                                ;
;       |alt_counter_f10ke:wysi_counter| ; 5 (5)       ; 4            ; 0           ; 0    ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |reg_16|lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 21    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 21    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 17    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:i_rtl_0 ;
+------------------------+---------+-----------------------------------+
; Parameter Name         ; Value   ; Type                              ;
+------------------------+---------+-----------------------------------+
; AUTO_CARRY_CHAINS      ; ON      ; AUTO_CARRY                        ;
; IGNORE_CARRY_BUFFERS   ; OFF     ; IGNORE_CARRY                      ;
; AUTO_CASCADE_CHAINS    ; ON      ; AUTO_CASCADE                      ;
; IGNORE_CASCADE_BUFFERS ; OFF     ; IGNORE_CASCADE                    ;
; LPM_WIDTH              ; 4       ; Untyped                           ;
; LPM_DIRECTION          ; UP      ; Untyped                           ;
; LPM_MODULUS            ; 0       ; Untyped                           ;
; LPM_AVALUE             ; UNUSED  ; Untyped                           ;
; LPM_SVALUE             ; UNUSED  ; Untyped                           ;
; DEVICE_FAMILY          ; ACEX1K  ; Untyped                           ;
; CARRY_CHAIN            ; MANUAL  ; Untyped                           ;
; CARRY_CHAIN_LENGTH     ; 48      ; CARRY_CHAIN_LENGTH                ;
; NOT_GATE_PUSH_BACK     ; ON      ; NOT_GATE_PUSH_BACK                ;
; CARRY_CNT_EN           ; SMART   ; Untyped                           ;
; LABWIDE_SCLR           ; ON      ; Untyped                           ;
; USE_NEW_VERSION        ; TRUE    ; Untyped                           ;
; CBXI_PARAMETER         ; NOTHING ; Untyped                           ;
+------------------------+---------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/8位十进制乘法器/reg_16/reg_16.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 19 15:44:12 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off reg_16 -c reg_16
Info: Found 2 design units, including 1 entities, in source file reg_16.vhd
    Info: Found design unit 1: reg_16-arc_reg_16
    Info: Found entity 1: reg_16
Info: Elaborating entity "reg_16" for the top level hierarchy
Warning: VHDL Process Statement warning at reg_16.vhd(17): signal "clr" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "i[0]~4"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Implemented 55 device resources after synthesis - the final resource count might be different
    Info: Implemented 12 input pins
    Info: Implemented 17 output pins
    Info: Implemented 26 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Dec 19 15:44:14 2012
    Info: Elapsed time: 00:00:03