reg_16.tan.rpt

8位十进制乘法器

; N/A           ; None        ; -4.300 ns ; r16_in[8] ; reg16[15]                                               ; r16_clk  ;
; N/A           ; None        ; -4.500 ns ; r16_in[7] ; reg16[14]                                               ; r16_clk  ;
; N/A           ; None        ; -4.500 ns ; r16_in[4] ; reg16[11]                                               ; r16_clk  ;
+---------------+-------------+-----------+-----------+---------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 19 15:44:20 2012
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off reg_16 -c reg_16
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "r16_clk" is an undefined clock
Info: Clock "r16_clk" has Internal fmax of 149.25 MHz between source register "lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2]" and destination register "cout~reg0" (period= 6.7 ns)
    Info: + Longest register to register delay is 5.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_C35; Fanout = 5; REG Node = 'lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2]'
        Info: 2: + IC(0.300 ns) + CELL(1.700 ns) = 2.000 ns; Loc. = LC1_C35; Fanout = 17; COMB Node = 'reduce_nor~18'
        Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 4.300 ns; Loc. = LC1_C36; Fanout = 1; COMB Node = 'cout~2'
        Info: 4: + IC(0.300 ns) + CELL(1.000 ns) = 5.600 ns; Loc. = LC2_C36; Fanout = 1; REG Node = 'cout~reg0'
        Info: Total cell delay = 4.100 ns ( 73.21 % )
        Info: Total interconnect delay = 1.500 ns ( 26.79 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "r16_clk" to destination register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 22; CLK Node = 'r16_clk'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_C36; Fanout = 1; REG Node = 'cout~reg0'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: - Longest clock path from clock "r16_clk" to source register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 22; CLK Node = 'r16_clk'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_C35; Fanout = 5; REG Node = 'lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[2]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "reg16[14]" (data pin = "r16_in[7]", clock pin = "r16_clk") is 6.400 ns
    Info: + Longest pin to register delay is 8.200 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_97; Fanout = 1; PIN Node = 'r16_in[7]'
        Info: 2: + IC(2.500 ns) + CELL(0.800 ns) = 8.200 ns; Loc. = LC8_C32; Fanout = 1; REG Node = 'reg16[14]'
        Info: Total cell delay = 5.700 ns ( 69.51 % )
        Info: Total interconnect delay = 2.500 ns ( 30.49 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "r16_clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 22; CLK Node = 'r16_clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC8_C32; Fanout = 1; REG Node = 'reg16[14]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: tco from clock "r16_clk" to destination pin "r16_out[0]" through register "reg16[0]" is 11.500 ns
    Info: + Longest clock path from clock "r16_clk" to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 22; CLK Node = 'r16_clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_D35; Fanout = 1; REG Node = 'reg16[0]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 8.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_D35; Fanout = 1; REG Node = 'reg16[0]'
        Info: 2: + IC(2.300 ns) + CELL(6.300 ns) = 8.600 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'r16_out[0]'
        Info: Total cell delay = 6.300 ns ( 73.26 % )
        Info: Total interconnect delay = 2.300 ns ( 26.74 % )
Info: th for register "reg16[7]" (data pin = "r16_in[0]", clock pin = "r16_clk") is 0.700 ns
    Info: + Longest clock path from clock "r16_clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 22; CLK Node = 'r16_clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC3_D35; Fanout = 2; REG Node = 'reg16[7]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_56; Fanout = 1; PIN Node = 'r16_in[0]'
        Info: 2: + IC(0.200 ns) + CELL(0.800 ns) = 3.000 ns; Loc. = LC3_D35; Fanout = 2; REG Node = 'reg16[7]'
        Info: Total cell delay = 2.800 ns ( 93.33 % )
        Info: Total interconnect delay = 0.200 ns ( 6.67 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Dec 19 15:44:21 2012
    Info: Elapsed time: 00:00:02