cnt10.vhd

来自「8位十进制乘法器」· VHDL 代码 · 共 22 行

Library ieee;  --0到9计数器
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_1164.all;
Entity cnt10 is
Port (clk,clr: in std_logic;
            q: out std_logic_vector(3 downto 0));
end cnt10;
architecture behav of cnt10 is
begin
   process(clk,clr)
     variable cqi: std_logic_vector(3 downto 0);
   begin
    if clr='1' then cqi:="0000";
      elsif clk'event and clk='1' then
          if cqi=9 then cqi:="0000";
             else  cqi:=cqi+1;
          end if;
    end if;
  q<=cqi;
end process;
end behav;