📄 cnt10.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cqi\[3\] cqi\[3\] 200.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 200.0 MHz between source register \"cqi\[3\]\" and destination register \"cqi\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.400 ns + Longest register register " "Info: + Longest register to register delay is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cqi\[3\] 1 REG LC5_D13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_D13; Fanout = 3; REG Node = 'cqi\[3\]'" { } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "" { cqi[3] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 1.400 ns cqi\[3\] 2 REG LC5_D13 3 " "Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 1.400 ns; Loc. = LC5_D13; Fanout = 3; REG Node = 'cqi\[3\]'" { } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "1.400 ns" { cqi[3] cqi[3] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.100 ns 78.57 % " "Info: Total cell delay = 1.100 ns ( 78.57 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns 21.43 % " "Info: Total interconnect delay = 0.300 ns ( 21.43 % )" { } { } 0} } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "1.400 ns" { cqi[3] cqi[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.400 ns" { cqi[3] cqi[3] } { 0.000ns 0.300ns } { 0.000ns 1.100ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 4; CLK Node = 'clk'" { } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "" { clk } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns cqi\[3\] 2 REG LC5_D13 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_D13; Fanout = 3; REG Node = 'cqi\[3\]'" { } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "0.400 ns" { clk cqi[3] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0} } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "2.400 ns" { clk cqi[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cqi[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 4; CLK Node = 'clk'" { } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "" { clk } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns cqi\[3\] 2 REG LC5_D13 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_D13; Fanout = 3; REG Node = 'cqi\[3\]'" { } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "0.400 ns" { clk cqi[3] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0} } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "2.400 ns" { clk cqi[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cqi[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "2.400 ns" { clk cqi[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cqi[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "2.400 ns" { clk cqi[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cqi[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } } } 0} } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "1.400 ns" { cqi[3] cqi[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.400 ns" { cqi[3] cqi[3] } { 0.000ns 0.300ns } { 0.000ns 1.100ns } } } { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "2.400 ns" { clk cqi[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cqi[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "2.400 ns" { clk cqi[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cqi[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "" { cqi[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { cqi[3] } { } { } } } { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[3\] cqi\[3\] 10.600 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[3\]\" through register \"cqi\[3\]\" is 10.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 4 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 4; CLK Node = 'clk'" { } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "" { clk } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 5 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns cqi\[3\] 2 REG LC5_D13 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_D13; Fanout = 3; REG Node = 'cqi\[3\]'" { } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "0.400 ns" { clk cqi[3] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0} } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "2.400 ns" { clk cqi[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cqi[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.700 ns + Longest register pin " "Info: + Longest register to pin delay is 7.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cqi\[3\] 1 REG LC5_D13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_D13; Fanout = 3; REG Node = 'cqi\[3\]'" { } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "" { cqi[3] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(6.300 ns) 7.700 ns q\[3\] 2 PIN PIN_90 0 " "Info: 2: + IC(1.400 ns) + CELL(6.300 ns) = 7.700 ns; Loc. = PIN_90; Fanout = 0; PIN Node = 'q\[3\]'" { } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "7.700 ns" { cqi[3] q[3] } "NODE_NAME" } "" } } { "cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 81.82 % " "Info: Total cell delay = 6.300 ns ( 81.82 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 18.18 % " "Info: Total interconnect delay = 1.400 ns ( 18.18 % )" { } { } 0} } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "7.700 ns" { cqi[3] q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.700 ns" { cqi[3] q[3] } { 0.000ns 1.400ns } { 0.000ns 6.300ns } } } } 0} } { { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "2.400 ns" { clk cqi[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out cqi[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" "" { Report "F:/8位十进制乘法器/cnt10/db/cnt10_cmp.qrpt" Compiler "cnt10" "UNKNOWN" "V1" "F:/8位十进制乘法器/cnt10/db/cnt10.quartus_db" { Floorplan "F:/8位十进制乘法器/cnt10/" "" "7.700 ns" { cqi[3] q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.700 ns" { cqi[3] q[3] } { 0.000ns 1.400ns } { 0.000ns 6.300ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 19 15:40:33 2012 " "Info: Processing ended: Wed Dec 19 15:40:33 2012" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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