bcd_b.vhd

来自「8位十进制乘法器」· VHDL 代码 · 共 21 行

Library ieee;  --（0到99）BCD码转二进制码
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_1164.all;
Entity BCD_B is
Port ( a: in std_logic_vector(7 downto 0);
       q: out std_logic_vector(7 downto 0));
end BCD_B;
architecture behav of BCD_B is
 signal a1,a2,a3,a4,cq: std_logic_vector(7 downto 0);
begin
   process(a)
   begin
      a1<="0000"&a(3 downto 0);
      a2<="0000"&a(7 downto 4);
      a3<=a2(6 downto 0)&'0';
      a4<=a2(4 downto 0)&"000";
      cq<=a4+a3+a1;
  q<=cq;
end process;
end behav;