📄 bcd_b.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--E3_cs_buffer[1] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] at LC1_D7
--operation mode is arithmetic
E3_cs_buffer[1] = a[4] $ a[1];
--E3L01 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~104 at LC1_D7
--operation mode is arithmetic
E3L01 = a[4] $ a[1];
--E3_cout[1] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1] at LC1_D7
--operation mode is arithmetic
E3_cout[1] = CARRY(a[4] & a[1]);
--E3_cs_buffer[2] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] at LC2_D7
--operation mode is arithmetic
E3_cs_buffer[2] = a[2] $ a[5] $ E3_cout[1];
--E3L21 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~105 at LC2_D7
--operation mode is arithmetic
E3L21 = a[2] $ a[5] $ E3_cout[1];
--E3_cout[2] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2] at LC2_D7
--operation mode is arithmetic
E3_cout[2] = CARRY(a[2] & (a[5] # E3_cout[1]) # !a[2] & a[5] & E3_cout[1]);
--E3_cs_buffer[3] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] at LC3_D7
--operation mode is arithmetic
E3_cs_buffer[3] = a[3] $ A1L11 $ E3_cout[2];
--E3L41 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~106 at LC3_D7
--operation mode is arithmetic
E3L41 = a[3] $ A1L11 $ E3_cout[2];
--E3_cout[3] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3] at LC3_D7
--operation mode is arithmetic
E3_cout[3] = CARRY(a[3] & (A1L11 # E3_cout[2]) # !a[3] & A1L11 & E3_cout[2]);
--E3_cs_buffer[4] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] at LC4_D7
--operation mode is arithmetic
E3_cs_buffer[4] = A1L21 $ A1L31 $ E3_cout[3];
--E3L61 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~107 at LC4_D7
--operation mode is arithmetic
E3L61 = A1L21 $ A1L31 $ E3_cout[3];
--E3_cout[4] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4] at LC4_D7
--operation mode is arithmetic
E3_cout[4] = CARRY(E3_cout[3] & (A1L21 $ A1L31));
--E3_cs_buffer[5] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] at LC5_D7
--operation mode is arithmetic
E3_cs_buffer[5] = a[6] $ A1L41 $ E3_cout[4];
--E3L81 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~108 at LC5_D7
--operation mode is arithmetic
E3L81 = a[6] $ A1L41 $ E3_cout[4];
--E3_cout[5] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5] at LC5_D7
--operation mode is arithmetic
E3_cout[5] = CARRY(E3_cout[4] & (a[6] $ A1L41));
--E3_cs_buffer[6] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] at LC6_D7
--operation mode is arithmetic
E3_cs_buffer[6] = a[7] $ A1L51 $ E3_cout[5];
--E3L02 is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~109 at LC6_D7
--operation mode is arithmetic
E3L02 = a[7] $ A1L51 $ E3_cout[5];
--E3_cout[6] is lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6] at LC6_D7
--operation mode is arithmetic
E3_cout[6] = CARRY(E3_cout[5] & (a[7] $ A1L51));
--A1L01 is add~258 at LC1_D15
--operation mode is normal
A1L01 = a[7] & a[6] & (a[5] # a[4]);
--A1L61 is add~264 at LC1_D15
--operation mode is normal
A1L61 = a[7] & a[6] & (a[5] # a[4]);
--C1_unreg_res_node[7] is lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[7] at LC7_D7
--operation mode is normal
C1_unreg_res_node[7] = E3_cout[6] $ A1L01;
--C1L3 is lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[7]~17 at LC7_D7
--operation mode is normal
C1L3 = E3_cout[6] $ A1L01;
--A1L11 is add~259 at LC3_D5
--operation mode is normal
A1L11 = a[6] $ a[4];
--A1L71 is add~265 at LC3_D5
--operation mode is normal
A1L71 = a[6] $ a[4];
--A1L21 is add~260 at LC1_D9
--operation mode is normal
A1L21 = a[6] & a[4];
--A1L81 is add~266 at LC1_D9
--operation mode is normal
A1L81 = a[6] & a[4];
--A1L31 is add~261 at LC8_D7
--operation mode is normal
A1L31 = a[7] $ a[5];
--A1L91 is add~267 at LC8_D7
--operation mode is normal
A1L91 = a[7] $ a[5];
--A1L41 is add~262 at LC2_D5
--operation mode is normal
A1L41 = a[7] & (a[5] # a[6] & a[4]) # !a[7] & a[5] & a[6] & a[4];
--A1L02 is add~268 at LC2_D5
--operation mode is normal
A1L02 = a[7] & (a[5] # a[6] & a[4]) # !a[7] & a[5] & a[6] & a[4];
--A1L51 is add~263 at LC1_D5
--operation mode is normal
A1L51 = a[6] & (a[5] & (a[7] # a[4]) # !a[5] & a[7] & a[4]);
--A1L12 is add~269 at LC1_D5
--operation mode is normal
A1L12 = a[6] & (a[5] & (a[7] # a[4]) # !a[5] & a[7] & a[4]);
--a[0] is a[0] at PIN_125
--operation mode is input
a[0] = INPUT();
--a[7] is a[7] at PIN_54
--operation mode is input
a[7] = INPUT();
--a[6] is a[6] at PIN_126
--operation mode is input
a[6] = INPUT();
--a[5] is a[5] at PIN_56
--operation mode is input
a[5] = INPUT();
--a[4] is a[4] at PIN_124
--operation mode is input
a[4] = INPUT();
--a[1] is a[1] at PIN_55
--operation mode is input
a[1] = INPUT();
--a[2] is a[2] at PIN_89
--operation mode is input
a[2] = INPUT();
--a[3] is a[3] at PIN_88
--operation mode is input
a[3] = INPUT();
--q[0] is q[0] at PIN_96
--operation mode is output
q[0] = OUTPUT(A1L42);
--q[1] is q[1] at PIN_92
--operation mode is output
q[1] = OUTPUT(E3_cs_buffer[1]);
--q[2] is q[2] at PIN_20
--operation mode is output
q[2] = OUTPUT(E3_cs_buffer[2]);
--q[3] is q[3] at PIN_91
--operation mode is output
q[3] = OUTPUT(E3_cs_buffer[3]);
--q[4] is q[4] at PIN_21
--operation mode is output
q[4] = OUTPUT(E3_cs_buffer[4]);
--q[5] is q[5] at PIN_90
--operation mode is output
q[5] = OUTPUT(E3_cs_buffer[5]);
--q[6] is q[6] at PIN_22
--operation mode is output
q[6] = OUTPUT(E3_cs_buffer[6]);
--q[7] is q[7] at PIN_23
--operation mode is output
q[7] = OUTPUT(C1_unreg_res_node[7]);
--A1L42 is q[0]~0 at LC4_C16
--operation mode is normal
A1L42 = a[0];
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