📄 b_bcd.tan.qmsg

📁 8位十进制乘法器
💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register out_a\[3\] 140.85 MHz 7.1 ns Internal " "Info: Clock \"clk\" has Internal fmax of 140.85 MHz between source register \"lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"out_a\[3\]\" (period= 7.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC7_C5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_C5; Fanout = 5; REG Node = 'lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 2.000 ns add~301 2 COMB LC2_C5 4 " "Info: 2: + IC(0.300 ns) + CELL(1.700 ns) = 2.000 ns; Loc. = LC2_C5; Fanout = 4; COMB Node = 'add~301'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "2.000 ns" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] add~301 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.600 ns) 4.700 ns out_a~2855 3 COMB LC4_C6 4 " "Info: 3: + IC(1.100 ns) + CELL(1.600 ns) = 4.700 ns; Loc. = LC4_C6; Fanout = 4; COMB Node = 'out_a~2855'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "2.700 ns" { add~301 out_a~2855 } "NODE_NAME" } "" } } { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 6.000 ns out_a\[3\] 4 REG LC5_C6 5 " "Info: 4: + IC(0.300 ns) + CELL(1.000 ns) = 6.000 ns; Loc. = LC5_C6; Fanout = 5; REG Node = 'out_a\[3\]'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "1.300 ns" { out_a~2855 out_a[3] } "NODE_NAME" } "" } } { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.300 ns 71.67 % " "Info: Total cell delay = 4.300 ns ( 71.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 28.33 % " "Info: Total interconnect delay = 1.700 ns ( 28.33 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "6.000 ns" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] add~301 out_a~2855 out_a[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.000 ns" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] add~301 out_a~2855 out_a[3] } { 0.000ns 0.300ns 1.100ns 0.300ns } { 0.000ns 1.700ns 1.600ns 1.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 39 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 39; CLK Node = 'clk'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "" { clk } "NODE_NAME" } "" } } { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns out_a\[3\] 2 REG LC5_C6 5 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_C6; Fanout = 5; REG Node = 'out_a\[3\]'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "0.400 ns" { clk out_a[3] } "NODE_NAME" } "" } } { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "2.400 ns" { clk out_a[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out out_a[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 39 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 39; CLK Node = 'clk'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "" { clk } "NODE_NAME" } "" } } { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC7_C5 5 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_C5; Fanout = 5; REG Node = 'lpm_counter:i_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "0.400 ns" { clk lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "2.400 ns" { clk lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "2.400 ns" { clk out_a[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out out_a[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "2.400 ns" { clk lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 13 -1 0 } }  } 0}  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "6.000 ns" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] add~301 out_a~2855 out_a[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.000 ns" { lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] add~301 out_a~2855 out_a[3] } { 0.000ns 0.300ns 1.100ns 0.300ns } { 0.000ns 1.700ns 1.600ns 1.000ns } } } { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "2.400 ns" { clk out_a[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out out_a[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "2.400 ns" { clk lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[7\] out_a\[7\] 11.500 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[7\]\" through register \"out_a\[7\]\" is 11.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 39 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 39; CLK Node = 'clk'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "" { clk } "NODE_NAME" } "" } } { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns out_a\[7\] 2 REG LC6_C4 5 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_C4; Fanout = 5; REG Node = 'out_a\[7\]'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "0.400 ns" { clk out_a[7] } "NODE_NAME" } "" } } { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns 83.33 % " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns 16.67 % " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "2.400 ns" { clk out_a[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out out_a[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.600 ns + Longest register pin " "Info: + Longest register to pin delay is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out_a\[7\] 1 REG LC6_C4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_C4; Fanout = 5; REG Node = 'out_a\[7\]'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "" { out_a[7] } "NODE_NAME" } "" } } { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(6.300 ns) 8.600 ns q\[7\] 2 PIN PIN_18 0 " "Info: 2: + IC(2.300 ns) + CELL(6.300 ns) = 8.600 ns; Loc. = PIN_18; Fanout = 0; PIN Node = 'q\[7\]'" {  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "8.600 ns" { out_a[7] q[7] } "NODE_NAME" } "" } } { "B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns 73.26 % " "Info: Total cell delay = 6.300 ns ( 73.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns 26.74 % " "Info: Total interconnect delay = 2.300 ns ( 26.74 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "8.600 ns" { out_a[7] q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { out_a[7] q[7] } { 0.000ns 2.300ns } { 0.000ns 6.300ns } } }  } 0}  } { { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "2.400 ns" { clk out_a[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.400 ns" { clk clk~out out_a[7] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } } } { "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" "" { Report "F:/8位十进制乘法器/B_BCD/db/B_BCD_cmp.qrpt" Compiler "B_BCD" "UNKNOWN" "V1" "F:/8位十进制乘法器/B_BCD/db/B_BCD.quartus_db" { Floorplan "F:/8位十进制乘法器/B_BCD/" "" "8.600 ns" { out_a[7] q[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.600 ns" { out_a[7] q[7] } { 0.000ns 2.300ns } { 0.000ns 6.300ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 19 15:35:03 2012 " "Info: Processing ended: Wed Dec 19 15:35:03 2012" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
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