b_bcd.vhd

来自「8位十进制乘法器」· VHDL 代码 · 共 34 行

Library ieee;    --16位二进制转BCD码（0到9999）
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_1164.all;
Entity B_BCD is
Port ( clk,ena:in std_logic;
         a: in std_logic_vector(15 downto 0);
         q: out std_logic_vector(15 downto 0));
end B_BCD;
architecture behav of B_BCD is  
begin
  process(clk,a)
  variable i: std_logic_vector(4 downto 0);
  variable in_a,out_a :std_logic_vector(15 downto 0);
begin
 if ena='0'then 
    in_a:=a; i:="00000"; out_a:="0000000000000000"; 
 elsif clk'event and clk='1' then
     if i="10000" then out_a:=out_a;     
    else out_a:=out_a(14 downto 0)&in_a(15);
         in_a:=in_a(14 downto 0)&'0'; 
         i:=i+1;
        if i<"10000" then
          if out_a( 3 downto  0)>4 then out_a( 3 downto  0):=out_a( 3 downto  0)+3;
          end if; 
          if out_a( 7 downto  4)>4 then out_a( 7 downto  4):=out_a( 7 downto  4)+3;
          end if;
          if out_a(11 downto  8)>4 then out_a(11 downto  8):=out_a(11 downto  8)+3;
          end if; 
          if out_a(15 downto 12)>4 then out_a(15 downto 12):=out_a(15 downto 12)+3;
          end if;
        end if;     end if;   end if ;
 q<=out_a;
end process;  end behav;