📄 multi_8x8.tan.qmsg

📁 8位十进制乘法器
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_a1 register register cnt10:u1\|cqi\[3\] cnt10:u1\|cqi\[3\] 200.0 MHz Internal " "Info: Clock \"clk_a1\" Internal fmax is restricted to 200.0 MHz between source register \"cnt10:u1\|cqi\[3\]\" and destination register \"cnt10:u1\|cqi\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.400 ns + Longest register register " "Info: + Longest register to register delay is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt10:u1\|cqi\[3\] 1 REG LC4_B7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B7; Fanout = 9; REG Node = 'cnt10:u1\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 1.400 ns cnt10:u1\|cqi\[3\] 2 REG LC4_B7 9 " "Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 1.400 ns; Loc. = LC4_B7; Fanout = 9; REG Node = 'cnt10:u1\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "1.400 ns" { cnt10:u1|cqi[3] cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.100 ns 78.57 % " "Info: Total cell delay = 1.100 ns ( 78.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns 21.43 % " "Info: Total interconnect delay = 0.300 ns ( 21.43 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "1.400 ns" { cnt10:u1|cqi[3] cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.400 ns" { cnt10:u1|cqi[3] cnt10:u1|cqi[3] } { 0.000ns 0.300ns } { 0.000ns 1.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_a1 destination 9.100 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_a1\" to destination register is 9.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns clk_a1 1 CLK PIN_19 4 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_19; Fanout = 4; CLK Node = 'clk_a1'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { clk_a1 } "NODE_NAME" } "" } } { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.200 ns) + CELL(0.000 ns) 9.100 ns cnt10:u1\|cqi\[3\] 2 REG LC4_B7 9 " "Info: 2: + IC(4.200 ns) + CELL(0.000 ns) = 9.100 ns; Loc. = LC4_B7; Fanout = 9; REG Node = 'cnt10:u1\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "4.200 ns" { clk_a1 cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns 53.85 % " "Info: Total cell delay = 4.900 ns ( 53.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns 46.15 % " "Info: Total interconnect delay = 4.200 ns ( 46.15 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.100 ns" { clk_a1 cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.100 ns" { clk_a1 clk_a1~out cnt10:u1|cqi[3] } { 0.000ns 0.000ns 4.200ns } { 0.000ns 4.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_a1 source 9.100 ns - Longest register " "Info: - Longest clock path from clock \"clk_a1\" to source register is 9.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns clk_a1 1 CLK PIN_19 4 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_19; Fanout = 4; CLK Node = 'clk_a1'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { clk_a1 } "NODE_NAME" } "" } } { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.200 ns) + CELL(0.000 ns) 9.100 ns cnt10:u1\|cqi\[3\] 2 REG LC4_B7 9 " "Info: 2: + IC(4.200 ns) + CELL(0.000 ns) = 9.100 ns; Loc. = LC4_B7; Fanout = 9; REG Node = 'cnt10:u1\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "4.200 ns" { clk_a1 cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns 53.85 % " "Info: Total cell delay = 4.900 ns ( 53.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns 46.15 % " "Info: Total interconnect delay = 4.200 ns ( 46.15 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.100 ns" { clk_a1 cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.100 ns" { clk_a1 clk_a1~out cnt10:u1|cqi[3] } { 0.000ns 0.000ns 4.200ns } { 0.000ns 4.900ns 0.000ns } } }  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.100 ns" { clk_a1 cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.100 ns" { clk_a1 clk_a1~out cnt10:u1|cqi[3] } { 0.000ns 0.000ns 4.200ns } { 0.000ns 4.900ns 0.000ns } } } { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.100 ns" { clk_a1 cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.100 ns" { clk_a1 clk_a1~out cnt10:u1|cqi[3] } { 0.000ns 0.000ns 4.200ns } { 0.000ns 4.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "1.400 ns" { cnt10:u1|cqi[3] cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.400 ns" { cnt10:u1|cqi[3] cnt10:u1|cqi[3] } { 0.000ns 0.300ns } { 0.000ns 1.100ns } } } { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.100 ns" { clk_a1 cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.100 ns" { clk_a1 clk_a1~out cnt10:u1|cqi[3] } { 0.000ns 0.000ns 4.200ns } { 0.000ns 4.900ns 0.000ns } } } { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.100 ns" { clk_a1 cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.100 ns" { clk_a1 clk_a1~out cnt10:u1|cqi[3] } { 0.000ns 0.000ns 4.200ns } { 0.000ns 4.900ns 0.000ns } } }  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { cnt10:u1|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { cnt10:u1|cqi[3] } {  } {  } } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_a0 register register cnt10:u2\|cqi\[3\] cnt10:u2\|cqi\[3\] 200.0 MHz Internal " "Info: Clock \"clk_a0\" Internal fmax is restricted to 200.0 MHz between source register \"cnt10:u2\|cqi\[3\]\" and destination register \"cnt10:u2\|cqi\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.400 ns + Longest register register " "Info: + Longest register to register delay is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt10:u2\|cqi\[3\] 1 REG LC5_B5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_B5; Fanout = 5; REG Node = 'cnt10:u2\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 1.400 ns cnt10:u2\|cqi\[3\] 2 REG LC5_B5 5 " "Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 1.400 ns; Loc. = LC5_B5; Fanout = 5; REG Node = 'cnt10:u2\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "1.400 ns" { cnt10:u2|cqi[3] cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.100 ns 78.57 % " "Info: Total cell delay = 1.100 ns ( 78.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns 21.43 % " "Info: Total interconnect delay = 0.300 ns ( 21.43 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "1.400 ns" { cnt10:u2|cqi[3] cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.400 ns" { cnt10:u2|cqi[3] cnt10:u2|cqi[3] } { 0.000ns 0.300ns } { 0.000ns 1.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_a0 destination 9.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_a0\" to destination register is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns clk_a0 1 CLK PIN_18 4 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_18; Fanout = 4; CLK Node = 'clk_a0'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { clk_a0 } "NODE_NAME" } "" } } { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(0.000 ns) 9.000 ns cnt10:u2\|cqi\[3\] 2 REG LC5_B5 5 " "Info: 2: + IC(4.100 ns) + CELL(0.000 ns) = 9.000 ns; Loc. = LC5_B5; Fanout = 5; REG Node = 'cnt10:u2\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "4.100 ns" { clk_a0 cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns 54.44 % " "Info: Total cell delay = 4.900 ns ( 54.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.100 ns 45.56 % " "Info: Total interconnect delay = 4.100 ns ( 45.56 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.000 ns" { clk_a0 cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { clk_a0 clk_a0~out cnt10:u2|cqi[3] } { 0.000ns 0.000ns 4.100ns } { 0.000ns 4.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_a0 source 9.000 ns - Longest register " "Info: - Longest clock path from clock \"clk_a0\" to source register is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns clk_a0 1 CLK PIN_18 4 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_18; Fanout = 4; CLK Node = 'clk_a0'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { clk_a0 } "NODE_NAME" } "" } } { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(0.000 ns) 9.000 ns cnt10:u2\|cqi\[3\] 2 REG LC5_B5 5 " "Info: 2: + IC(4.100 ns) + CELL(0.000 ns) = 9.000 ns; Loc. = LC5_B5; Fanout = 5; REG Node = 'cnt10:u2\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "4.100 ns" { clk_a0 cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns 54.44 % " "Info: Total cell delay = 4.900 ns ( 54.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.100 ns 45.56 % " "Info: Total interconnect delay = 4.100 ns ( 45.56 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.000 ns" { clk_a0 cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { clk_a0 clk_a0~out cnt10:u2|cqi[3] } { 0.000ns 0.000ns 4.100ns } { 0.000ns 4.900ns 0.000ns } } }  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.000 ns" { clk_a0 cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { clk_a0 clk_a0~out cnt10:u2|cqi[3] } { 0.000ns 0.000ns 4.100ns } { 0.000ns 4.900ns 0.000ns } } } { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.000 ns" { clk_a0 cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { clk_a0 clk_a0~out cnt10:u2|cqi[3] } { 0.000ns 0.000ns 4.100ns } { 0.000ns 4.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "1.400 ns" { cnt10:u2|cqi[3] cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.400 ns" { cnt10:u2|cqi[3] cnt10:u2|cqi[3] } { 0.000ns 0.300ns } { 0.000ns 1.100ns } } } { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.000 ns" { clk_a0 cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { clk_a0 clk_a0~out cnt10:u2|cqi[3] } { 0.000ns 0.000ns 4.100ns } { 0.000ns 4.900ns 0.000ns } } } { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.000 ns" { clk_a0 cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.000 ns" { clk_a0 clk_a0~out cnt10:u2|cqi[3] } { 0.000ns 0.000ns 4.100ns } { 0.000ns 4.900ns 0.000ns } } }  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { cnt10:u2|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { cnt10:u2|cqi[3] } {  } {  } } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_b1 register register cnt10:u3\|cqi\[3\] cnt10:u3\|cqi\[3\] 200.0 MHz Internal " "Info: Clock \"clk_b1\" Internal fmax is restricted to 200.0 MHz between source register \"cnt10:u3\|cqi\[3\]\" and destination register \"cnt10:u3\|cqi\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.400 ns + Longest register register " "Info: + Longest register to register delay is 1.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt10:u3\|cqi\[3\] 1 REG LC4_E8 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_E8; Fanout = 9; REG Node = 'cnt10:u3\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 1.400 ns cnt10:u3\|cqi\[3\] 2 REG LC4_E8 9 " "Info: 2: + IC(0.300 ns) + CELL(1.100 ns) = 1.400 ns; Loc. = LC4_E8; Fanout = 9; REG Node = 'cnt10:u3\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "1.400 ns" { cnt10:u3|cqi[3] cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.100 ns 78.57 % " "Info: Total cell delay = 1.100 ns ( 78.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns 21.43 % " "Info: Total interconnect delay = 0.300 ns ( 21.43 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "1.400 ns" { cnt10:u3|cqi[3] cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.400 ns" { cnt10:u3|cqi[3] cnt10:u3|cqi[3] } { 0.000ns 0.300ns } { 0.000ns 1.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_b1 destination 9.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_b1\" to destination register is 9.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns clk_b1 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'clk_b1'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { clk_b1 } "NODE_NAME" } "" } } { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 9.400 ns cnt10:u3\|cqi\[3\] 2 REG LC4_E8 9 " "Info: 2: + IC(4.500 ns) + CELL(0.000 ns) = 9.400 ns; Loc. = LC4_E8; Fanout = 9; REG Node = 'cnt10:u3\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "4.500 ns" { clk_b1 cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns 52.13 % " "Info: Total cell delay = 4.900 ns ( 52.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns 47.87 % " "Info: Total interconnect delay = 4.500 ns ( 47.87 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.400 ns" { clk_b1 cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.400 ns" { clk_b1 clk_b1~out cnt10:u3|cqi[3] } { 0.000ns 0.000ns 4.500ns } { 0.000ns 4.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_b1 source 9.400 ns - Longest register " "Info: - Longest clock path from clock \"clk_b1\" to source register is 9.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns clk_b1 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_17; Fanout = 4; CLK Node = 'clk_b1'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { clk_b1 } "NODE_NAME" } "" } } { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 9.400 ns cnt10:u3\|cqi\[3\] 2 REG LC4_E8 9 " "Info: 2: + IC(4.500 ns) + CELL(0.000 ns) = 9.400 ns; Loc. = LC4_E8; Fanout = 9; REG Node = 'cnt10:u3\|cqi\[3\]'" {  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "4.500 ns" { clk_b1 cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns 52.13 % " "Info: Total cell delay = 4.900 ns ( 52.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns 47.87 % " "Info: Total interconnect delay = 4.500 ns ( 47.87 % )" {  } {  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.400 ns" { clk_b1 cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.400 ns" { clk_b1 clk_b1~out cnt10:u3|cqi[3] } { 0.000ns 0.000ns 4.500ns } { 0.000ns 4.900ns 0.000ns } } }  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.400 ns" { clk_b1 cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.400 ns" { clk_b1 clk_b1~out cnt10:u3|cqi[3] } { 0.000ns 0.000ns 4.500ns } { 0.000ns 4.900ns 0.000ns } } } { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.400 ns" { clk_b1 cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.400 ns" { clk_b1 clk_b1~out cnt10:u3|cqi[3] } { 0.000ns 0.000ns 4.500ns } { 0.000ns 4.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "1.400 ns" { cnt10:u3|cqi[3] cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "1.400 ns" { cnt10:u3|cqi[3] cnt10:u3|cqi[3] } { 0.000ns 0.300ns } { 0.000ns 1.100ns } } } { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.400 ns" { clk_b1 cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.400 ns" { clk_b1 clk_b1~out cnt10:u3|cqi[3] } { 0.000ns 0.000ns 4.500ns } { 0.000ns 4.900ns 0.000ns } } } { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "9.400 ns" { clk_b1 cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "9.400 ns" { clk_b1 clk_b1~out cnt10:u3|cqi[3] } { 0.000ns 0.000ns 4.500ns } { 0.000ns 4.900ns 0.000ns } } }  } 0}  } { { "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" "" { Report "F:/8位十进制乘法器/multi_8x8/db/multi_8x8_cmp.qrpt" Compiler "multi_8x8" "UNKNOWN" "V1" "F:/8位十进制乘法器/multi_8x8/db/multi_8x8.quartus_db" { Floorplan "F:/8位十进制乘法器/multi_8x8/" "" "" { cnt10:u3|cqi[3] } "NODE_NAME" } "" } } { "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus50/bin/Technology_Viewer.qrui" "" { cnt10:u3|cqi[3] } {  } {  } } } { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 11 -1 0 } }  } 0}
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