multi_8x8.map.qmsg

8位十进制乘法器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 19 21:42:31 2012 " "Info: Processing started: Wed Dec 19 21:42:31 2012" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off multi_8x8 -c multi_8x8 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off multi_8x8 -c multi_8x8" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../reg_16/reg_16.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../reg_16/reg_16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg_16-arc_reg_16 " "Info: Found design unit 1: reg_16-arc_reg_16" {  } { { "../reg_16/reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 reg_16 " "Info: Found entity 1: reg_16" {  } { { "../reg_16/reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../reg_8/reg_8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../reg_8/reg_8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg_8-arc_reg_8 " "Info: Found design unit 1: reg_8-arc_reg_8" {  } { { "../reg_8/reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 reg_8 " "Info: Found entity 1: reg_8" {  } { { "../reg_8/reg_8.vhd" "" { Text "F:/8位十进制乘法器/reg_8/reg_8.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../multi_1/multi_1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../multi_1/multi_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 multi_1-arc_multi_1 " "Info: Found design unit 1: multi_1-arc_multi_1" {  } { { "../multi_1/multi_1.vhd" "" { Text "F:/8位十进制乘法器/multi_1/multi_1.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 multi_1 " "Info: Found entity 1: multi_1" {  } { { "../multi_1/multi_1.vhd" "" { Text "F:/8位十进制乘法器/multi_1/multi_1.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../cnt10/cnt10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../cnt10/cnt10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt10-behav " "Info: Found design unit 1: cnt10-behav" {  } { { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt10 " "Info: Found entity 1: cnt10" {  } { { "../cnt10/cnt10.vhd" "" { Text "F:/8位十进制乘法器/cnt10/cnt10.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../BCD_B/BCD_B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../BCD_B/BCD_B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 BCD_B-behav " "Info: Found design unit 1: BCD_B-behav" {  } { { "../BCD_B/BCD_B.vhd" "" { Text "F:/8位十进制乘法器/BCD_B/BCD_B.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 BCD_B " "Info: Found entity 1: BCD_B" {  } { { "../BCD_B/BCD_B.vhd" "" { Text "F:/8位十进制乘法器/BCD_B/BCD_B.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../B_BCD/B_BCD.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../B_BCD/B_BCD.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 B_BCD-behav " "Info: Found design unit 1: B_BCD-behav" {  } { { "../B_BCD/B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 B_BCD " "Info: Found entity 1: B_BCD" {  } { { "../B_BCD/B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../adder_8/adder_8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../adder_8/adder_8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder_8-arc_adder_8 " "Info: Found design unit 1: adder_8-arc_adder_8" {  } { { "../adder_8/adder_8.vhd" "" { Text "F:/8位十进制乘法器/adder_8/adder_8.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 adder_8 " "Info: Found entity 1: adder_8" {  } { { "../adder_8/adder_8.vhd" "" { Text "F:/8位十进制乘法器/adder_8/adder_8.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "multi_8x8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file multi_8x8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 multi_8x8-arc_multi_8x8 " "Info: Found design unit 1: multi_8x8-arc_multi_8x8" {  } { { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 multi_8x8 " "Info: Found entity 1: multi_8x8" {  } { { "multi_8x8.vhd" "" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "multi_8x8 " "Info: Elaborating entity \"multi_8x8\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt10 cnt10:u1 " "Info: Elaborating entity \"cnt10\" for hierarchy \"cnt10:u1\"" {  } { { "multi_8x8.vhd" "u1" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 59 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BCD_B BCD_B:u5 " "Info: Elaborating entity \"BCD_B\" for hierarchy \"BCD_B:u5\"" {  } { { "multi_8x8.vhd" "u5" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 67 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a2 BCD_B.vhd(15) " "Warning: VHDL Process Statement warning at BCD_B.vhd(15): signal \"a2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "../BCD_B/BCD_B.vhd" "" { Text "F:/8位十进制乘法器/BCD_B/BCD_B.vhd" 15 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a2 BCD_B.vhd(16) " "Warning: VHDL Process Statement warning at BCD_B.vhd(16): signal \"a2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "../BCD_B/BCD_B.vhd" "" { Text "F:/8位十进制乘法器/BCD_B/BCD_B.vhd" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a4 BCD_B.vhd(17) " "Warning: VHDL Process Statement warning at BCD_B.vhd(17): signal \"a4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "../BCD_B/BCD_B.vhd" "" { Text "F:/8位十进制乘法器/BCD_B/BCD_B.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a3 BCD_B.vhd(17) " "Warning: VHDL Process Statement warning at BCD_B.vhd(17): signal \"a3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "../BCD_B/BCD_B.vhd" "" { Text "F:/8位十进制乘法器/BCD_B/BCD_B.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "a1 BCD_B.vhd(17) " "Warning: VHDL Process Statement warning at BCD_B.vhd(17): signal \"a1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "../BCD_B/BCD_B.vhd" "" { Text "F:/8位十进制乘法器/BCD_B/BCD_B.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cq BCD_B.vhd(18) " "Warning: VHDL Process Statement warning at BCD_B.vhd(18): signal \"cq\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "../BCD_B/BCD_B.vhd" "" { Text "F:/8位十进制乘法器/BCD_B/BCD_B.vhd" 18 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_8 reg_8:u7 " "Info: Elaborating entity \"reg_8\" for hierarchy \"reg_8:u7\"" {  } { { "multi_8x8.vhd" "u7" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 71 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "multi_1 multi_1:u8 " "Info: Elaborating entity \"multi_1\" for hierarchy \"multi_1:u8\"" {  } { { "multi_8x8.vhd" "u8" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 73 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder_8 adder_8:u9 " "Info: Elaborating entity \"adder_8\" for hierarchy \"adder_8:u9\"" {  } { { "multi_8x8.vhd" "u9" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 75 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg_16 reg_16:u10 " "Info: Elaborating entity \"reg_16\" for hierarchy \"reg_16:u10\"" {  } { { "multi_8x8.vhd" "u10" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 77 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clr reg_16.vhd(17) " "Warning: VHDL Process Statement warning at reg_16.vhd(17): signal \"clr\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "../reg_16/reg_16.vhd" "" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 17 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "B_BCD B_BCD:u11 " "Info: Elaborating entity \"B_BCD\" for hierarchy \"B_BCD:u11\"" {  } { { "multi_8x8.vhd" "u11" { Text "F:/8位十进制乘法器/multi_8x8/multi_8x8.vhd" 79 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "ena B_BCD.vhd(15) " "Warning: VHDL Process Statement warning at B_BCD.vhd(15): signal \"ena\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "../B_BCD/B_BCD.vhd" "" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 15 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "B_BCD:u11\|i\[0\]~0 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: \"B_BCD:u11\|i\[0\]~0\"" {  } { { "../B_BCD/B_BCD.vhd" "i\[0\]~0" { Text "F:/8位十进制乘法器/B_BCD/B_BCD.vhd" 12 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "reg_16:u10\|i\[0\]~4 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"reg_16:u10\|i\[0\]~4\"" {  } { { "../reg_16/reg_16.vhd" "i\[0\]~4" { Text "F:/8位十进制乘法器/reg_16/reg_16.vhd" 13 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "183 " "Info: Implemented 183 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "144 " "Info: Implemented 144 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 19 21:42:33 2012 " "Info: Processing ended: Wed Dec 19 21:42:33 2012" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}