multi_8x8.map.rpt

8位十进制乘法器

; STYLE                  ; FAST        ; Untyped                                  ;
; CBXI_PARAMETER         ; add_sub_4ih ; Untyped                                  ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                               ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                             ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                             ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                           ;
+------------------------+-------------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: adder_8:u9|lpm_add_sub:add_rtl_3 ;
+------------------------+-------------+--------------------------------------------+
; Parameter Name         ; Value       ; Type                                       ;
+------------------------+-------------+--------------------------------------------+
; LPM_WIDTH              ; 9           ; Untyped                                    ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                    ;
; LPM_DIRECTION          ; ADD         ; Untyped                                    ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                    ;
; LPM_PIPELINE           ; 0           ; Untyped                                    ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                    ;
; REGISTERED_AT_END      ; 0           ; Untyped                                    ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                    ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                    ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                    ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                         ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                                    ;
; USE_WYS                ; OFF         ; Untyped                                    ;
; STYLE                  ; FAST        ; Untyped                                    ;
; CBXI_PARAMETER         ; add_sub_5ih ; Untyped                                    ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                 ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                               ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                               ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                             ;
+------------------------+-------------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: BCD_B:u5|lpm_add_sub:add_rtl_4 ;
+------------------------+-------------+------------------------------------------+
; Parameter Name         ; Value       ; Type                                     ;
+------------------------+-------------+------------------------------------------+
; LPM_WIDTH              ; 8           ; Untyped                                  ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                                  ;
; LPM_DIRECTION          ; ADD         ; Untyped                                  ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                                  ;
; LPM_PIPELINE           ; 0           ; Untyped                                  ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                                  ;
; REGISTERED_AT_END      ; 0           ; Untyped                                  ;
; OPTIMIZE_FOR_SPEED     ; 1           ; Untyped                                  ;
; USE_CS_BUFFERS         ; 1           ; Untyped                                  ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                  ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                       ;
; DEVICE_FAMILY          ; ACEX1K      ; Untyped                                  ;
; USE_WYS                ; OFF         ; Untyped                                  ;
; STYLE                  ; FAST        ; Untyped                                  ;
; CBXI_PARAMETER         ; add_sub_4ih ; Untyped                                  ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                               ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                             ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                             ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                           ;
+------------------------+-------------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/8位十进制乘法器/multi_8x8/multi_8x8.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 19 21:42:31 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off multi_8x8 -c multi_8x8
Info: Found 2 design units, including 1 entities, in source file ../reg_16/reg_16.vhd
    Info: Found design unit 1: reg_16-arc_reg_16
    Info: Found entity 1: reg_16
Info: Found 2 design units, including 1 entities, in source file ../reg_8/reg_8.vhd
    Info: Found design unit 1: reg_8-arc_reg_8
    Info: Found entity 1: reg_8
Info: Found 2 design units, including 1 entities, in source file ../multi_1/multi_1.vhd
    Info: Found design unit 1: multi_1-arc_multi_1
    Info: Found entity 1: multi_1
Info: Found 2 design units, including 1 entities, in source file ../cnt10/cnt10.vhd
    Info: Found design unit 1: cnt10-behav
    Info: Found entity 1: cnt10
Info: Found 2 design units, including 1 entities, in source file ../BCD_B/BCD_B.vhd
    Info: Found design unit 1: BCD_B-behav
    Info: Found entity 1: BCD_B
Info: Found 2 design units, including 1 entities, in source file ../B_BCD/B_BCD.vhd
    Info: Found design unit 1: B_BCD-behav
    Info: Found entity 1: B_BCD
Info: Found 2 design units, including 1 entities, in source file ../adder_8/adder_8.vhd
    Info: Found design unit 1: adder_8-arc_adder_8
    Info: Found entity 1: adder_8
Info: Found 2 design units, including 1 entities, in source file multi_8x8.vhd
    Info: Found design unit 1: multi_8x8-arc_multi_8x8
    Info: Found entity 1: multi_8x8
Info: Elaborating entity "multi_8x8" for the top level hierarchy
Info: Elaborating entity "cnt10" for hierarchy "cnt10:u1"
Info: Elaborating entity "BCD_B" for hierarchy "BCD_B:u5"
Warning: VHDL Process Statement warning at BCD_B.vhd(15): signal "a2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at BCD_B.vhd(16): signal "a2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at BCD_B.vhd(17): signal "a4" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at BCD_B.vhd(17): signal "a3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at BCD_B.vhd(17): signal "a1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at BCD_B.vhd(18): signal "cq" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "reg_8" for hierarchy "reg_8:u7"
Info: Elaborating entity "multi_1" for hierarchy "multi_1:u8"
Info: Elaborating entity "adder_8" for hierarchy "adder_8:u9"
Info: Elaborating entity "reg_16" for hierarchy "reg_16:u10"
Warning: VHDL Process Statement warning at reg_16.vhd(17): signal "clr" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "B_BCD" for hierarchy "B_BCD:u11"
Warning: VHDL Process Statement warning at B_BCD.vhd(15): signal "ena" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "B_BCD:u11|i[0]~0"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "reg_16:u10|i[0]~4"
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Implemented 183 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 32 output pins
    Info: Implemented 144 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Processing ended: Wed Dec 19 21:42:33 2012
    Info: Elapsed time: 00:00:04