multi_8x8.map.eqn

8位十进制乘法器

--C2L6 is BCD_B:u6|add~263
--operation mode is normal

C2L6 = B3_cqi[0] $ B3_cqi[2];

--C2L21 is BCD_B:u6|add~269
--operation mode is normal

C2L21 = B3_cqi[0] $ B3_cqi[2];


--C1L1 is BCD_B:u5|add~258
--operation mode is normal

C1L1 = B1_cqi[0] $ B1_cqi[2];

--C1L7 is BCD_B:u5|add~264
--operation mode is normal

C1L7 = B1_cqi[0] $ B1_cqi[2];


--M3_cs_buffer[5] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M3_cs_buffer[5] = B1_cqi[2] $ C1L4 $ M3_cout[4];

--M3L81 is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~108
--operation mode is arithmetic

M3L81 = B1_cqi[2] $ C1L4 $ M3_cout[4];

--M3_cout[5] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M3_cout[5] = CARRY(M3_cout[4] & (B1_cqi[2] $ C1L4));


--D1_reg8[6] is reg_8:u7|reg8[6]
--operation mode is normal

D1_reg8[6]_lut_out = start & M3_cs_buffer[6] # !start & (D1_reg8[7]);
D1_reg8[6] = DFFEA(D1_reg8[6]_lut_out, clk, !clr, , , , );

--D1L51Q is reg_8:u7|reg8[6]~42
--operation mode is normal

D1L51Q = D1_reg8[6];


--H1_in_a[3] is B_BCD:u11|in_a[3]
--operation mode is normal

H1_in_a[3]_lut_out = H1_in_a[2];
H1_in_a[3] = DFFEA(H1_in_a[3]_lut_out, clk, , , H1L39, G1_reg16[3], !G1_cout);

--H1L11Q is B_BCD:u11|in_a[3]~35
--operation mode is normal

H1L11Q = H1_in_a[3];


--G1_reg16[4] is reg_16:u10|reg16[4]
--operation mode is normal

G1_reg16[4]_lut_out = G1_reg16[5];
G1_reg16[4] = DFFEA(G1_reg16[4]_lut_out, clk, !G1L2, , G1L7, , );

--G1L12Q is reg_16:u10|reg16[4]~70
--operation mode is normal

G1L12Q = G1_reg16[4];


--E1L1 is multi_1:u8|m1_out[0]~101
--operation mode is normal

E1L1 = B4_cqi[0] & D1_reg8[0];

--E1L2 is multi_1:u8|m1_out[0]~109
--operation mode is normal

E1L2 = B4_cqi[0] & D1_reg8[0];


--C1L2 is BCD_B:u5|add~259
--operation mode is normal

C1L2 = B1_cqi[0] & B1_cqi[2];

--C1L8 is BCD_B:u5|add~265
--operation mode is normal

C1L8 = B1_cqi[0] & B1_cqi[2];


--C1L3 is BCD_B:u5|add~260
--operation mode is normal

C1L3 = B1_cqi[1] $ B1_cqi[3];

--C1L9 is BCD_B:u5|add~266
--operation mode is normal

C1L9 = B1_cqi[1] $ B1_cqi[3];


--M3_cs_buffer[6] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

M3_cs_buffer[6] = B1_cqi[3] $ C1L5 $ M3_cout[5];

--M3L02 is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~109
--operation mode is arithmetic

M3L02 = B1_cqi[3] $ C1L5 $ M3_cout[5];

--M3_cout[6] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

M3_cout[6] = CARRY(M3_cout[5] & (B1_cqi[3] $ C1L5));


--D1_reg8[7] is reg_8:u7|reg8[7]
--operation mode is normal

D1_reg8[7]_lut_out = K1_unreg_res_node[7];
D1_reg8[7] = DFFEA(D1_reg8[7]_lut_out, clk, !clr, , start, , );

--D1L71Q is reg_8:u7|reg8[7]~43
--operation mode is normal

D1L71Q = D1_reg8[7];


--H1_in_a[2] is B_BCD:u11|in_a[2]
--operation mode is normal

H1_in_a[2]_lut_out = H1_in_a[1];
H1_in_a[2] = DFFEA(H1_in_a[2]_lut_out, clk, , , H1L39, G1_reg16[2], !G1_cout);

--H1L9Q is B_BCD:u11|in_a[2]~36
--operation mode is normal

H1L9Q = H1_in_a[2];


--G1_reg16[3] is reg_16:u10|reg16[3]
--operation mode is normal

G1_reg16[3]_lut_out = G1_reg16[4];
G1_reg16[3] = DFFEA(G1_reg16[3]_lut_out, clk, !G1L2, , G1L7, , );

--G1L91Q is reg_16:u10|reg16[3]~71
--operation mode is normal

G1L91Q = G1_reg16[3];


--C1L4 is BCD_B:u5|add~261
--operation mode is normal

C1L4 = B1_cqi[1] & (B1_cqi[3] # B1_cqi[0] & B1_cqi[2]) # !B1_cqi[1] & B1_cqi[3] & B1_cqi[0] & B1_cqi[2];

--C1L01 is BCD_B:u5|add~267
--operation mode is normal

C1L01 = B1_cqi[1] & (B1_cqi[3] # B1_cqi[0] & B1_cqi[2]) # !B1_cqi[1] & B1_cqi[3] & B1_cqi[0] & B1_cqi[2];


--H1_in_a[1] is B_BCD:u11|in_a[1]
--operation mode is normal

H1_in_a[1]_lut_out = H1_in_a[0];
H1_in_a[1] = DFFEA(H1_in_a[1]_lut_out, clk, , , H1L39, G1_reg16[1], !G1_cout);

--H1L7Q is B_BCD:u11|in_a[1]~37
--operation mode is normal

H1L7Q = H1_in_a[1];


--G1_reg16[2] is reg_16:u10|reg16[2]
--operation mode is normal

G1_reg16[2]_lut_out = G1_reg16[3];
G1_reg16[2] = DFFEA(G1_reg16[2]_lut_out, clk, !G1L2, , G1L7, , );

--G1L71Q is reg_16:u10|reg16[2]~72
--operation mode is normal

G1L71Q = G1_reg16[2];


--C1L5 is BCD_B:u5|add~262
--operation mode is normal

C1L5 = B1_cqi[2] & (B1_cqi[3] & (B1_cqi[1] # B1_cqi[0]) # !B1_cqi[3] & B1_cqi[1] & B1_cqi[0]);

--C1L11 is BCD_B:u5|add~268
--operation mode is normal

C1L11 = B1_cqi[2] & (B1_cqi[3] & (B1_cqi[1] # B1_cqi[0]) # !B1_cqi[3] & B1_cqi[1] & B1_cqi[0]);


--C1L6 is BCD_B:u5|add~263
--operation mode is normal

C1L6 = B1_cqi[3] & B1_cqi[2] & (B1_cqi[1] # B1_cqi[0]);

--C1L21 is BCD_B:u5|add~269
--operation mode is normal

C1L21 = B1_cqi[3] & B1_cqi[2] & (B1_cqi[1] # B1_cqi[0]);


--K1_unreg_res_node[7] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[7]
--operation mode is normal

K1_unreg_res_node[7] = M3_cout[6] $ C1L6;

--K1L3 is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[7]~17
--operation mode is normal

K1L3 = M3_cout[6] $ C1L6;


--H1_in_a[0] is B_BCD:u11|in_a[0]
--operation mode is normal

H1_in_a[0]_lut_out = GND;
H1_in_a[0] = DFFEA(H1_in_a[0]_lut_out, clk, , , H1L39, G1_reg16[0], !G1_cout);

--H1L5Q is B_BCD:u11|in_a[0]~38
--operation mode is normal

H1L5Q = H1_in_a[0];


--G1_reg16[1] is reg_16:u10|reg16[1]
--operation mode is normal

G1_reg16[1]_lut_out = G1_reg16[2];
G1_reg16[1] = DFFEA(G1_reg16[1]_lut_out, clk, !G1L2, , G1L7, , );

--G1L51Q is reg_16:u10|reg16[1]~73
--operation mode is normal

G1L51Q = G1_reg16[1];


--G1_reg16[0] is reg_16:u10|reg16[0]
--operation mode is normal

G1_reg16[0]_lut_out = G1_reg16[1];
G1_reg16[0] = DFFEA(G1_reg16[0]_lut_out, clk, !G1L2, , G1L7, , );

--G1L31Q is reg_16:u10|reg16[0]~74
--operation mode is normal

G1L31Q = G1_reg16[0];


--G1L3 is reg_16:u10|cout~2
--operation mode is normal

G1L3 = !G1L7;

--G1L6 is reg_16:u10|cout~5
--operation mode is normal

G1L6 = !G1L7;


--clk_a1 is clk_a1
--operation mode is input

clk_a1 = INPUT();


--clr is clr
--operation mode is input

clr = INPUT();


--clk_a0 is clk_a0
--operation mode is input

clk_a0 = INPUT();


--clk_b1 is clk_b1
--operation mode is input

clk_b1 = INPUT();


--clk_b0 is clk_b0
--operation mode is input

clk_b0 = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--start is start
--operation mode is input

start = INPUT();


--out_a1[0] is out_a1[0]
--operation mode is output

out_a1[0] = OUTPUT(B1_cqi[0]);


--out_a1[1] is out_a1[1]
--operation mode is output

out_a1[1] = OUTPUT(B1_cqi[1]);


--out_a1[2] is out_a1[2]
--operation mode is output

out_a1[2] = OUTPUT(B1_cqi[2]);


--out_a1[3] is out_a1[3]
--operation mode is output

out_a1[3] = OUTPUT(B1_cqi[3]);


--out_a0[0] is out_a0[0]
--operation mode is output

out_a0[0] = OUTPUT(B2_cqi[0]);


--out_a0[1] is out_a0[1]
--operation mode is output

out_a0[1] = OUTPUT(B2_cqi[1]);


--out_a0[2] is out_a0[2]
--operation mode is output

out_a0[2] = OUTPUT(B2_cqi[2]);


--out_a0[3] is out_a0[3]
--operation mode is output

out_a0[3] = OUTPUT(B2_cqi[3]);


--out_b1[0] is out_b1[0]
--operation mode is output

out_b1[0] = OUTPUT(B3_cqi[0]);


--out_b1[1] is out_b1[1]
--operation mode is output

out_b1[1] = OUTPUT(B3_cqi[1]);


--out_b1[2] is out_b1[2]
--operation mode is output

out_b1[2] = OUTPUT(B3_cqi[2]);


--out_b1[3] is out_b1[3]
--operation mode is output

out_b1[3] = OUTPUT(B3_cqi[3]);


--out_b0[0] is out_b0[0]
--operation mode is output

out_b0[0] = OUTPUT(B4_cqi[0]);


--out_b0[1] is out_b0[1]
--operation mode is output

out_b0[1] = OUTPUT(B4_cqi[1]);


--out_b0[2] is out_b0[2]
--operation mode is output

out_b0[2] = OUTPUT(B4_cqi[2]);


--out_b0[3] is out_b0[3]
--operation mode is output

out_b0[3] = OUTPUT(B4_cqi[3]);


--result[0] is result[0]
--operation mode is output

result[0] = OUTPUT(H1_out_a[0]);


--result[1] is result[1]
--operation mode is output

result[1] = OUTPUT(H1_out_a[1]);


--result[2] is result[2]
--operation mode is output

result[2] = OUTPUT(H1_out_a[2]);


--result[3] is result[3]
--operation mode is output

result[3] = OUTPUT(H1_out_a[3]);


--result[4] is result[4]
--operation mode is output

result[4] = OUTPUT(H1_out_a[4]);


--result[5] is result[5]
--operation mode is output

result[5] = OUTPUT(H1_out_a[5]);


--result[6] is result[6]
--operation mode is output

result[6] = OUTPUT(H1_out_a[6]);


--result[7] is result[7]
--operation mode is output

result[7] = OUTPUT(H1_out_a[7]);


--result[8] is result[8]
--operation mode is output

result[8] = OUTPUT(H1_out_a[8]);


--result[9] is result[9]
--operation mode is output

result[9] = OUTPUT(H1_out_a[9]);


--result[10] is result[10]
--operation mode is output

result[10] = OUTPUT(H1_out_a[10]);


--result[11] is result[11]
--operation mode is output

result[11] = OUTPUT(H1_out_a[11]);


--result[12] is result[12]
--operation mode is output

result[12] = OUTPUT(H1_out_a[12]);


--result[13] is result[13]
--operation mode is output

result[13] = OUTPUT(H1_out_a[13]);


--result[14] is result[14]
--operation mode is output

result[14] = OUTPUT(H1_out_a[14]);


--result[15] is result[15]
--operation mode is output

result[15] = OUTPUT(H1_out_a[15]);