multi_8x8.map.eqn

8位十进制乘法器

--operation mode is normal

E1L41 = D1_reg8[0] & M6_cs_buffer[6];


--D1_reg8[1] is reg_8:u7|reg8[1]
--operation mode is normal

D1_reg8[1]_lut_out = start & M3_cs_buffer[1] # !start & (D1_reg8[2]);
D1_reg8[1] = DFFEA(D1_reg8[1]_lut_out, clk, !clr, , , , );

--D1L5Q is reg_8:u7|reg8[1]~37
--operation mode is normal

D1L5Q = D1_reg8[1];


--C2L1 is BCD_B:u6|add~258
--operation mode is normal

C2L1 = B3_cqi[3] & B3_cqi[2] & (B3_cqi[1] # B3_cqi[0]);

--C2L7 is BCD_B:u6|add~264
--operation mode is normal

C2L7 = B3_cqi[3] & B3_cqi[2] & (B3_cqi[1] # B3_cqi[0]);


--K2_unreg_res_node[7] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[7]
--operation mode is normal

K2_unreg_res_node[7] = M6_cout[6] $ C2L1;

--K2L3 is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[7]~17
--operation mode is normal

K2L3 = M6_cout[6] $ C2L1;


--H1_in_a[8] is B_BCD:u11|in_a[8]
--operation mode is normal

H1_in_a[8]_lut_out = H1_in_a[7];
H1_in_a[8] = DFFEA(H1_in_a[8]_lut_out, clk, , , H1L39, G1_reg16[8], !G1_cout);

--H1L12Q is B_BCD:u11|in_a[8]~30
--operation mode is normal

H1L12Q = H1_in_a[8];


--G1_reg16[9] is reg_16:u10|reg16[9]
--operation mode is normal

G1_reg16[9]_lut_out = M9_cs_buffer[2];
G1_reg16[9] = DFFEA(G1_reg16[9]_lut_out, clk, !G1L2, , G1L7, , );

--G1L13Q is reg_16:u10|reg16[9]~65
--operation mode is normal

G1L13Q = G1_reg16[9];


--M9_cs_buffer[3] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

M9_cs_buffer[3] = G1_reg16[11] $ E1L7 $ M9_cout[2];

--M9L81 is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~159
--operation mode is arithmetic

M9L81 = G1_reg16[11] $ E1L7 $ M9_cout[2];

--M9_cout[3] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

M9_cout[3] = CARRY(G1_reg16[11] & (E1L7 # M9_cout[2]) # !G1_reg16[11] & E1L7 & M9_cout[2]);


--M6_cs_buffer[5] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M6_cs_buffer[5] = B3_cqi[2] $ C2L3 $ M6_cout[4];

--M6L81 is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~105
--operation mode is arithmetic

M6L81 = B3_cqi[2] $ C2L3 $ M6_cout[4];

--M6_cout[5] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M6_cout[5] = CARRY(M6_cout[4] & (B3_cqi[2] $ C2L3));


--E1L11 is multi_1:u8|m1_out[5]~96
--operation mode is normal

E1L11 = D1_reg8[0] & M6_cs_buffer[5];

--E1L21 is multi_1:u8|m1_out[5]~104
--operation mode is normal

E1L21 = D1_reg8[0] & M6_cs_buffer[5];


--M3_cs_buffer[1] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

M3_cs_buffer[1] = B1_cqi[0] $ B2_cqi[1];

--M3L01 is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~104
--operation mode is arithmetic

M3L01 = B1_cqi[0] $ B2_cqi[1];

--M3_cout[1] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

M3_cout[1] = CARRY(B1_cqi[0] & B2_cqi[1]);


--D1_reg8[2] is reg_8:u7|reg8[2]
--operation mode is normal

D1_reg8[2]_lut_out = start & M3_cs_buffer[2] # !start & (D1_reg8[3]);
D1_reg8[2] = DFFEA(D1_reg8[2]_lut_out, clk, !clr, , , , );

--D1L7Q is reg_8:u7|reg8[2]~38
--operation mode is normal

D1L7Q = D1_reg8[2];


--H1_in_a[7] is B_BCD:u11|in_a[7]
--operation mode is normal

H1_in_a[7]_lut_out = H1_in_a[6];
H1_in_a[7] = DFFEA(H1_in_a[7]_lut_out, clk, , , H1L39, G1_reg16[7], !G1_cout);

--H1L91Q is B_BCD:u11|in_a[7]~31
--operation mode is normal

H1L91Q = H1_in_a[7];


--G1_reg16[8] is reg_16:u10|reg16[8]
--operation mode is normal

G1_reg16[8]_lut_out = M9_cs_buffer[1];
G1_reg16[8] = DFFEA(G1_reg16[8]_lut_out, clk, !G1L2, , G1L7, , );

--G1L92Q is reg_16:u10|reg16[8]~66
--operation mode is normal

G1L92Q = G1_reg16[8];


--M9_cs_buffer[2] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

M9_cs_buffer[2] = G1_reg16[10] $ E1L5 $ M9_cout[1];

--M9L61 is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~160
--operation mode is arithmetic

M9L61 = G1_reg16[10] $ E1L5 $ M9_cout[1];

--M9_cout[2] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

M9_cout[2] = CARRY(G1_reg16[10] & (E1L5 # M9_cout[1]) # !G1_reg16[10] & E1L5 & M9_cout[1]);


--M6_cs_buffer[4] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M6_cs_buffer[4] = C2L4 $ C2L5 $ M6_cout[3];

--M6L61 is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~106
--operation mode is arithmetic

M6L61 = C2L4 $ C2L5 $ M6_cout[3];

--M6_cout[4] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M6_cout[4] = CARRY(M6_cout[3] & (C2L4 $ C2L5));


--E1L9 is multi_1:u8|m1_out[4]~97
--operation mode is normal

E1L9 = D1_reg8[0] & M6_cs_buffer[4];

--E1L01 is multi_1:u8|m1_out[4]~105
--operation mode is normal

E1L01 = D1_reg8[0] & M6_cs_buffer[4];


--C2L2 is BCD_B:u6|add~259
--operation mode is normal

C2L2 = B3_cqi[2] & (B3_cqi[3] & (B3_cqi[1] # B3_cqi[0]) # !B3_cqi[3] & B3_cqi[1] & B3_cqi[0]);

--C2L8 is BCD_B:u6|add~265
--operation mode is normal

C2L8 = B3_cqi[2] & (B3_cqi[3] & (B3_cqi[1] # B3_cqi[0]) # !B3_cqi[3] & B3_cqi[1] & B3_cqi[0]);


--M3_cs_buffer[2] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

M3_cs_buffer[2] = B2_cqi[2] $ B1_cqi[1] $ M3_cout[1];

--M3L21 is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~105
--operation mode is arithmetic

M3L21 = B2_cqi[2] $ B1_cqi[1] $ M3_cout[1];

--M3_cout[2] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

M3_cout[2] = CARRY(B2_cqi[2] & (B1_cqi[1] # M3_cout[1]) # !B2_cqi[2] & B1_cqi[1] & M3_cout[1]);


--D1_reg8[3] is reg_8:u7|reg8[3]
--operation mode is normal

D1_reg8[3]_lut_out = start & M3_cs_buffer[3] # !start & (D1_reg8[4]);
D1_reg8[3] = DFFEA(D1_reg8[3]_lut_out, clk, !clr, , , , );

--D1L9Q is reg_8:u7|reg8[3]~39
--operation mode is normal

D1L9Q = D1_reg8[3];


--H1_in_a[6] is B_BCD:u11|in_a[6]
--operation mode is normal

H1_in_a[6]_lut_out = H1_in_a[5];
H1_in_a[6] = DFFEA(H1_in_a[6]_lut_out, clk, , , H1L39, G1_reg16[6], !G1_cout);

--H1L71Q is B_BCD:u11|in_a[6]~32
--operation mode is normal

H1L71Q = H1_in_a[6];


--G1_reg16[7] is reg_16:u10|reg16[7]
--operation mode is normal

G1_reg16[7]_lut_out = M9_cs_buffer[0];
G1_reg16[7] = DFFEA(G1_reg16[7]_lut_out, clk, !G1L2, , G1L7, , );

--G1L72Q is reg_16:u10|reg16[7]~67
--operation mode is normal

G1L72Q = G1_reg16[7];


--M9_cs_buffer[1] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

M9_cs_buffer[1] = G1_reg16[9] $ E1L3 $ M9_cout[0];

--M9L41 is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~161
--operation mode is arithmetic

M9L41 = G1_reg16[9] $ E1L3 $ M9_cout[0];

--M9_cout[1] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

M9_cout[1] = CARRY(G1_reg16[9] & (E1L3 # M9_cout[0]) # !G1_reg16[9] & E1L3 & M9_cout[0]);


--M6_cs_buffer[3] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

M6_cs_buffer[3] = B4_cqi[3] $ C2L6 $ M6_cout[2];

--M6L41 is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~107
--operation mode is arithmetic

M6L41 = B4_cqi[3] $ C2L6 $ M6_cout[2];

--M6_cout[3] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

M6_cout[3] = CARRY(B4_cqi[3] & (C2L6 # M6_cout[2]) # !B4_cqi[3] & C2L6 & M6_cout[2]);


--E1L7 is multi_1:u8|m1_out[3]~98
--operation mode is normal

E1L7 = D1_reg8[0] & M6_cs_buffer[3];

--E1L8 is multi_1:u8|m1_out[3]~106
--operation mode is normal

E1L8 = D1_reg8[0] & M6_cs_buffer[3];


--C2L3 is BCD_B:u6|add~260
--operation mode is normal

C2L3 = B3_cqi[1] & (B3_cqi[3] # B3_cqi[0] & B3_cqi[2]) # !B3_cqi[1] & B3_cqi[3] & B3_cqi[0] & B3_cqi[2];

--C2L9 is BCD_B:u6|add~266
--operation mode is normal

C2L9 = B3_cqi[1] & (B3_cqi[3] # B3_cqi[0] & B3_cqi[2]) # !B3_cqi[1] & B3_cqi[3] & B3_cqi[0] & B3_cqi[2];


--M3_cs_buffer[3] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

M3_cs_buffer[3] = B2_cqi[3] $ C1L1 $ M3_cout[2];

--M3L41 is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~106
--operation mode is arithmetic

M3L41 = B2_cqi[3] $ C1L1 $ M3_cout[2];

--M3_cout[3] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

M3_cout[3] = CARRY(B2_cqi[3] & (C1L1 # M3_cout[2]) # !B2_cqi[3] & C1L1 & M3_cout[2]);


--D1_reg8[4] is reg_8:u7|reg8[4]
--operation mode is normal

D1_reg8[4]_lut_out = start & M3_cs_buffer[4] # !start & (D1_reg8[5]);
D1_reg8[4] = DFFEA(D1_reg8[4]_lut_out, clk, !clr, , , , );

--D1L11Q is reg_8:u7|reg8[4]~40
--operation mode is normal

D1L11Q = D1_reg8[4];


--H1_in_a[5] is B_BCD:u11|in_a[5]
--operation mode is normal

H1_in_a[5]_lut_out = H1_in_a[4];
H1_in_a[5] = DFFEA(H1_in_a[5]_lut_out, clk, , , H1L39, G1_reg16[5], !G1_cout);

--H1L51Q is B_BCD:u11|in_a[5]~33
--operation mode is normal

H1L51Q = H1_in_a[5];


--G1_reg16[6] is reg_16:u10|reg16[6]
--operation mode is normal

G1_reg16[6]_lut_out = G1_reg16[7];
G1_reg16[6] = DFFEA(G1_reg16[6]_lut_out, clk, !G1L2, , G1L7, , );

--G1L52Q is reg_16:u10|reg16[6]~68
--operation mode is normal

G1L52Q = G1_reg16[6];


--M9_cs_buffer[0] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic

M9_cs_buffer[0] = G1_reg16[8] $ E1L1;

--M9L21 is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~162
--operation mode is arithmetic

M9L21 = G1_reg16[8] $ E1L1;

--M9_cout[0] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

M9_cout[0] = CARRY(G1_reg16[8] & E1L1);


--M6_cs_buffer[2] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

M6_cs_buffer[2] = B4_cqi[2] $ B3_cqi[1] $ M6_cout[1];

--M6L21 is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~108
--operation mode is arithmetic

M6L21 = B4_cqi[2] $ B3_cqi[1] $ M6_cout[1];

--M6_cout[2] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

M6_cout[2] = CARRY(B4_cqi[2] & (B3_cqi[1] # M6_cout[1]) # !B4_cqi[2] & B3_cqi[1] & M6_cout[1]);


--E1L5 is multi_1:u8|m1_out[2]~99
--operation mode is normal

E1L5 = D1_reg8[0] & M6_cs_buffer[2];

--E1L6 is multi_1:u8|m1_out[2]~107
--operation mode is normal

E1L6 = D1_reg8[0] & M6_cs_buffer[2];


--C2L4 is BCD_B:u6|add~261
--operation mode is normal

C2L4 = B3_cqi[0] & B3_cqi[2];

--C2L01 is BCD_B:u6|add~267
--operation mode is normal

C2L01 = B3_cqi[0] & B3_cqi[2];


--C2L5 is BCD_B:u6|add~262
--operation mode is normal

C2L5 = B3_cqi[1] $ B3_cqi[3];

--C2L11 is BCD_B:u6|add~268
--operation mode is normal

C2L11 = B3_cqi[1] $ B3_cqi[3];


--M3_cs_buffer[4] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M3_cs_buffer[4] = C1L2 $ C1L3 $ M3_cout[3];

--M3L61 is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~107
--operation mode is arithmetic

M3L61 = C1L2 $ C1L3 $ M3_cout[3];

--M3_cout[4] is BCD_B:u5|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M3_cout[4] = CARRY(M3_cout[3] & (C1L2 $ C1L3));


--D1_reg8[5] is reg_8:u7|reg8[5]
--operation mode is normal

D1_reg8[5]_lut_out = start & M3_cs_buffer[5] # !start & (D1_reg8[6]);
D1_reg8[5] = DFFEA(D1_reg8[5]_lut_out, clk, !clr, , , , );

--D1L31Q is reg_8:u7|reg8[5]~41
--operation mode is normal

D1L31Q = D1_reg8[5];


--H1_in_a[4] is B_BCD:u11|in_a[4]
--operation mode is normal

H1_in_a[4]_lut_out = H1_in_a[3];
H1_in_a[4] = DFFEA(H1_in_a[4]_lut_out, clk, , , H1L39, G1_reg16[4], !G1_cout);

--H1L31Q is B_BCD:u11|in_a[4]~34
--operation mode is normal

H1L31Q = H1_in_a[4];


--G1_reg16[5] is reg_16:u10|reg16[5]
--operation mode is normal

G1_reg16[5]_lut_out = G1_reg16[6];
G1_reg16[5] = DFFEA(G1_reg16[5]_lut_out, clk, !G1L2, , G1L7, , );

--G1L32Q is reg_16:u10|reg16[5]~69
--operation mode is normal

G1L32Q = G1_reg16[5];


--M6_cs_buffer[1] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

M6_cs_buffer[1] = B3_cqi[0] $ B4_cqi[1];

--M6L01 is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~109
--operation mode is arithmetic

M6L01 = B3_cqi[0] $ B4_cqi[1];

--M6_cout[1] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

M6_cout[1] = CARRY(B3_cqi[0] & B4_cqi[1]);


--E1L3 is multi_1:u8|m1_out[1]~100
--operation mode is normal

E1L3 = D1_reg8[0] & M6_cs_buffer[1];

--E1L4 is multi_1:u8|m1_out[1]~108
--operation mode is normal

E1L4 = D1_reg8[0] & M6_cs_buffer[1];