multi_8x8.map.eqn

8位十进制乘法器

--P2L31Q is B_BCD:u11|lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~4
--operation mode is clrb_cntr

P2L31Q = P2_q[0];

--P2L3 is B_BCD:u11|lpm_counter:i_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

P2L3 = CARRY(P2_q[0]);


--H1L1 is B_BCD:u11|add~301
--operation mode is normal

H1L1 = P2_q[3] & P2_q[2] & P2_q[1] & P2_q[0];

--H1L2 is B_BCD:u11|add~302
--operation mode is normal

H1L2 = P2_q[3] & P2_q[2] & P2_q[1] & P2_q[0];


--H1L63 is B_BCD:u11|LessThan~201
--operation mode is normal

H1L63 = H1_out_a[1] & (H1_out_a[0] # H1_in_a[15]);

--H1L44 is B_BCD:u11|LessThan~209
--operation mode is normal

H1L44 = H1_out_a[1] & (H1_out_a[0] # H1_in_a[15]);


--H1L58 is B_BCD:u11|out_a~2855
--operation mode is normal

H1L58 = H1_out_a[2] & (P2_q[4] $ !H1L1) # !H1_out_a[2] & H1L63 & (P2_q[4] $ !H1L1);

--H1L98 is B_BCD:u11|out_a~2875
--operation mode is normal

H1L98 = H1_out_a[2] & (P2_q[4] $ !H1L1) # !H1_out_a[2] & H1L63 & (P2_q[4] $ !H1L1);


--G1L2 is reg_16:u10|cout~0
--operation mode is normal

G1L2 = clr # start;

--G1L5 is reg_16:u10|cout~4
--operation mode is normal

G1L5 = clr # start;


--P1_q[2] is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

P1_q[2]_lut_out = (P1_q[2] $ (P1L9 & P1L5)) & VCC;
P1_q[2] = DFFEA(P1_q[2]_lut_out, clk, !start, , , , );

--P1L71Q is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|q[2]~0
--operation mode is clrb_cntr

P1L71Q = P1_q[2];

--P1L7 is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

P1L7 = CARRY(P1_q[2] & (P1L5));


--P1_q[1] is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

P1_q[1]_lut_out = (P1_q[1] $ (P1L9 & P1L3)) & VCC;
P1_q[1] = DFFEA(P1_q[1]_lut_out, clk, !start, , , , );

--P1L51Q is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is clrb_cntr

P1L51Q = P1_q[1];

--P1L5 is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

P1L5 = CARRY(P1_q[1] & (P1L3));


--P1_q[0] is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

P1_q[0]_lut_out = (P1L9 $ P1_q[0]) & VCC;
P1_q[0] = DFFEA(P1_q[0]_lut_out, clk, !start, , , , );

--P1L31Q is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|q[0]~2
--operation mode is clrb_cntr

P1L31Q = P1_q[0];

--P1L3 is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

P1L3 = CARRY(P1_q[0]);


--P1_q[3] is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

P1_q[3]_lut_out = (P1_q[3] $ (P1L9 & P1L7)) & VCC;
P1_q[3] = DFFEA(P1_q[3]_lut_out, clk, !start, , , , );

--P1L91Q is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is clrb_cntr

P1L91Q = P1_q[3];


--G1L7 is reg_16:u10|reduce_nor~18
--operation mode is normal

G1L7 = P1_q[2] # P1_q[1] # P1_q[0] # !P1_q[3];

--G1L9 is reg_16:u10|reduce_nor~20
--operation mode is normal

G1L9 = P1_q[2] # P1_q[1] # P1_q[0] # !P1_q[3];


--H1L49 is B_BCD:u11|reduce_nor~25
--operation mode is normal

H1L49 = P2_q[2] # P2_q[1];

--H1L59 is B_BCD:u11|reduce_nor~26
--operation mode is normal

H1L59 = P2_q[2] # P2_q[1];


--H1L39 is B_BCD:u11|reduce_nor~0
--operation mode is normal

H1L39 = P2_q[0] # P2_q[3] # H1L49 # !P2_q[4];

--H1L69 is B_BCD:u11|reduce_nor~27
--operation mode is normal

H1L69 = P2_q[0] # P2_q[3] # H1L49 # !P2_q[4];


--H1L73 is B_BCD:u11|LessThan~202
--operation mode is normal

H1L73 = H1_out_a[0] # H1_in_a[15];

--H1L54 is B_BCD:u11|LessThan~210
--operation mode is normal

H1L54 = H1_out_a[0] # H1_in_a[15];


--H1L83 is B_BCD:u11|LessThan~203
--operation mode is normal

H1L83 = H1_out_a[5] & (H1_out_a[3] # H1_out_a[4]);

--H1L64 is B_BCD:u11|LessThan~211
--operation mode is normal

H1L64 = H1_out_a[5] & (H1_out_a[3] # H1_out_a[4]);


--H1L68 is B_BCD:u11|out_a~2856
--operation mode is normal

H1L68 = H1_out_a[6] & (P2_q[4] $ !H1L1) # !H1_out_a[6] & H1L83 & (P2_q[4] $ !H1L1);

--H1L09 is B_BCD:u11|out_a~2876
--operation mode is normal

H1L09 = H1_out_a[6] & (P2_q[4] $ !H1L1) # !H1_out_a[6] & H1L83 & (P2_q[4] $ !H1L1);


--H1L93 is B_BCD:u11|LessThan~204
--operation mode is normal

H1L93 = H1_out_a[3] # H1_out_a[4];

--H1L74 is B_BCD:u11|LessThan~212
--operation mode is normal

H1L74 = H1_out_a[3] # H1_out_a[4];


--H1L04 is B_BCD:u11|LessThan~205
--operation mode is normal

H1L04 = H1_out_a[9] & (H1_out_a[7] # H1_out_a[8]);

--H1L84 is B_BCD:u11|LessThan~213
--operation mode is normal

H1L84 = H1_out_a[9] & (H1_out_a[7] # H1_out_a[8]);


--H1L78 is B_BCD:u11|out_a~2857
--operation mode is normal

H1L78 = H1_out_a[10] & (P2_q[4] $ !H1L1) # !H1_out_a[10] & H1L04 & (P2_q[4] $ !H1L1);

--H1L19 is B_BCD:u11|out_a~2877
--operation mode is normal

H1L19 = H1_out_a[10] & (P2_q[4] $ !H1L1) # !H1_out_a[10] & H1L04 & (P2_q[4] $ !H1L1);


--H1L14 is B_BCD:u11|LessThan~206
--operation mode is normal

H1L14 = H1_out_a[7] # H1_out_a[8];

--H1L94 is B_BCD:u11|LessThan~214
--operation mode is normal

H1L94 = H1_out_a[7] # H1_out_a[8];


--H1L24 is B_BCD:u11|LessThan~207
--operation mode is normal

H1L24 = H1_out_a[13] & (H1_out_a[11] # H1_out_a[12]);

--H1L05 is B_BCD:u11|LessThan~215
--operation mode is normal

H1L05 = H1_out_a[13] & (H1_out_a[11] # H1_out_a[12]);


--H1L88 is B_BCD:u11|out_a~2858
--operation mode is normal

H1L88 = H1_out_a[14] & (P2_q[4] $ !H1L1) # !H1_out_a[14] & H1L24 & (P2_q[4] $ !H1L1);

--H1L29 is B_BCD:u11|out_a~2878
--operation mode is normal

H1L29 = H1_out_a[14] & (P2_q[4] $ !H1L1) # !H1_out_a[14] & H1L24 & (P2_q[4] $ !H1L1);


--H1L34 is B_BCD:u11|LessThan~208
--operation mode is normal

H1L34 = H1_out_a[11] # H1_out_a[12];

--H1L15 is B_BCD:u11|LessThan~216
--operation mode is normal

H1L15 = H1_out_a[11] # H1_out_a[12];


--H1_in_a[13] is B_BCD:u11|in_a[13]
--operation mode is normal

H1_in_a[13]_lut_out = H1_in_a[12];
H1_in_a[13] = DFFEA(H1_in_a[13]_lut_out, clk, , , H1L39, G1_reg16[13], !G1_cout);

--H1L13Q is B_BCD:u11|in_a[13]~25
--operation mode is normal

H1L13Q = H1_in_a[13];


--G1_reg16[14] is reg_16:u10|reg16[14]
--operation mode is normal

G1_reg16[14]_lut_out = M9_cs_buffer[7];
G1_reg16[14] = DFFEA(G1_reg16[14]_lut_out, clk, !G1L2, , G1L7, , );

--G1L14Q is reg_16:u10|reg16[14]~60
--operation mode is normal

G1L14Q = G1_reg16[14];


--G1L8 is reg_16:u10|reduce_nor~19
--operation mode is normal

G1L8 = P1_q[1] # P1_q[0];

--G1L01 is reg_16:u10|reduce_nor~21
--operation mode is normal

G1L01 = P1_q[1] # P1_q[0];


--P1L9 is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~0
--operation mode is normal

P1L9 = !clr & (P1_q[2] # G1L8 # !P1_q[3]);

--P1L01 is reg_16:u10|lpm_counter:i_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~54
--operation mode is normal

P1L01 = !clr & (P1_q[2] # G1L8 # !P1_q[3]);


--H1_in_a[12] is B_BCD:u11|in_a[12]
--operation mode is normal

H1_in_a[12]_lut_out = H1_in_a[11];
H1_in_a[12] = DFFEA(H1_in_a[12]_lut_out, clk, , , H1L39, G1_reg16[12], !G1_cout);

--H1L92Q is B_BCD:u11|in_a[12]~26
--operation mode is normal

H1L92Q = H1_in_a[12];


--G1_reg16[13] is reg_16:u10|reg16[13]
--operation mode is normal

G1_reg16[13]_lut_out = M9_cs_buffer[6];
G1_reg16[13] = DFFEA(G1_reg16[13]_lut_out, clk, !G1L2, , G1L7, , );

--G1L93Q is reg_16:u10|reg16[13]~61
--operation mode is normal

G1L93Q = G1_reg16[13];


--M9_cs_buffer[7] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

M9_cs_buffer[7] = G1_reg16[15] $ E1L51 $ M9_cout[6];

--M9L62 is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~155
--operation mode is arithmetic

M9L62 = G1_reg16[15] $ E1L51 $ M9_cout[6];

--M9_cout[7] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

M9_cout[7] = CARRY(G1_reg16[15] & (E1L51 # M9_cout[6]) # !G1_reg16[15] & E1L51 & M9_cout[6]);


--H1_in_a[11] is B_BCD:u11|in_a[11]
--operation mode is normal

H1_in_a[11]_lut_out = H1_in_a[10];
H1_in_a[11] = DFFEA(H1_in_a[11]_lut_out, clk, , , H1L39, G1_reg16[11], !G1_cout);

--H1L72Q is B_BCD:u11|in_a[11]~27
--operation mode is normal

H1L72Q = H1_in_a[11];


--G1_reg16[12] is reg_16:u10|reg16[12]
--operation mode is normal

G1_reg16[12]_lut_out = M9_cs_buffer[5];
G1_reg16[12] = DFFEA(G1_reg16[12]_lut_out, clk, !G1L2, , G1L7, , );

--G1L73Q is reg_16:u10|reg16[12]~62
--operation mode is normal

G1L73Q = G1_reg16[12];


--M9_cs_buffer[6] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

M9_cs_buffer[6] = G1_reg16[14] $ E1L31 $ M9_cout[5];

--M9L42 is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~156
--operation mode is arithmetic

M9L42 = G1_reg16[14] $ E1L31 $ M9_cout[5];

--M9_cout[6] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

M9_cout[6] = CARRY(G1_reg16[14] & (E1L31 # M9_cout[5]) # !G1_reg16[14] & E1L31 & M9_cout[5]);


--H1_in_a[10] is B_BCD:u11|in_a[10]
--operation mode is normal

H1_in_a[10]_lut_out = H1_in_a[9];
H1_in_a[10] = DFFEA(H1_in_a[10]_lut_out, clk, , , H1L39, G1_reg16[10], !G1_cout);

--H1L52Q is B_BCD:u11|in_a[10]~28
--operation mode is normal

H1L52Q = H1_in_a[10];


--G1_reg16[11] is reg_16:u10|reg16[11]
--operation mode is normal

G1_reg16[11]_lut_out = M9_cs_buffer[4];
G1_reg16[11] = DFFEA(G1_reg16[11]_lut_out, clk, !G1L2, , G1L7, , );

--G1L53Q is reg_16:u10|reg16[11]~63
--operation mode is normal

G1L53Q = G1_reg16[11];


--M9_cs_buffer[5] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M9_cs_buffer[5] = G1_reg16[13] $ E1L11 $ M9_cout[4];

--M9L22 is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~157
--operation mode is arithmetic

M9L22 = G1_reg16[13] $ E1L11 $ M9_cout[4];

--M9_cout[5] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M9_cout[5] = CARRY(G1_reg16[13] & (E1L11 # M9_cout[4]) # !G1_reg16[13] & E1L11 & M9_cout[4]);


--D1_reg8[0] is reg_8:u7|reg8[0]
--operation mode is normal

D1_reg8[0]_lut_out = start & B2_cqi[0] # !start & (D1_reg8[1]);
D1_reg8[0] = DFFEA(D1_reg8[0]_lut_out, clk, !clr, , , , );

--D1L3Q is reg_8:u7|reg8[0]~36
--operation mode is normal

D1L3Q = D1_reg8[0];


--E1L51 is multi_1:u8|m1_out[7]~94
--operation mode is normal

E1L51 = D1_reg8[0] & K2_unreg_res_node[7];

--E1L61 is multi_1:u8|m1_out[7]~102
--operation mode is normal

E1L61 = D1_reg8[0] & K2_unreg_res_node[7];


--H1_in_a[9] is B_BCD:u11|in_a[9]
--operation mode is normal

H1_in_a[9]_lut_out = H1_in_a[8];
H1_in_a[9] = DFFEA(H1_in_a[9]_lut_out, clk, , , H1L39, G1_reg16[9], !G1_cout);

--H1L32Q is B_BCD:u11|in_a[9]~29
--operation mode is normal

H1L32Q = H1_in_a[9];


--G1_reg16[10] is reg_16:u10|reg16[10]
--operation mode is normal

G1_reg16[10]_lut_out = M9_cs_buffer[3];
G1_reg16[10] = DFFEA(G1_reg16[10]_lut_out, clk, !G1L2, , G1L7, , );

--G1L33Q is reg_16:u10|reg16[10]~64
--operation mode is normal

G1L33Q = G1_reg16[10];


--M9_cs_buffer[4] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M9_cs_buffer[4] = G1_reg16[12] $ E1L9 $ M9_cout[3];

--M9L02 is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~158
--operation mode is arithmetic

M9L02 = G1_reg16[12] $ E1L9 $ M9_cout[3];

--M9_cout[4] is adder_8:u9|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M9_cout[4] = CARRY(G1_reg16[12] & (E1L9 # M9_cout[3]) # !G1_reg16[12] & E1L9 & M9_cout[3]);


--M6_cs_buffer[6] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

M6_cs_buffer[6] = B3_cqi[3] $ C2L2 $ M6_cout[5];

--M6L02 is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~104
--operation mode is arithmetic

M6L02 = B3_cqi[3] $ C2L2 $ M6_cout[5];

--M6_cout[6] is BCD_B:u6|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

M6_cout[6] = CARRY(M6_cout[5] & (B3_cqi[3] $ C2L2));


--E1L31 is multi_1:u8|m1_out[6]~95
--operation mode is normal

E1L31 = D1_reg8[0] & M6_cs_buffer[6];

--E1L41 is multi_1:u8|m1_out[6]~103