multi_8x8.vhd

8位十进制乘法器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity multi_8x8 is          
port(clk,clk_a1,clk_a0,clk_b1,clk_b0,clr,start:in std_logic;
            out_a1,out_a0,out_b1,out_b0: buffer std_logic_vector(3 downto 0);
            result: out std_logic_vector(15 downto 0));
end multi_8x8;
architecture arc_multi_8x8 of multi_8x8 is    

component cnt10   --调用0到9计数器声明
Port (clk,clr: in std_logic;
            q: out std_logic_vector(3 downto 0));
end component;

component BCD_B   --调用0到99）BCD码转二进制码声明
Port ( a: in std_logic_vector(7 downto 0);
       q: out std_logic_vector(7 downto 0));
end component;

component B_BCD  --调用16位二进制转BCD码（0到9999）声明
Port ( clk,ena:in std_logic;
         a: in std_logic_vector(15 downto 0);
         q: out std_logic_vector(15 downto 0));
end component;

component multi_1      --调用1位乘法器声明
port(m1_x:in std_logic;
     m1_y:in std_logic_vector(7 downto 0);
     m1_out:out std_logic_vector(7 downto 0));
end component;

component adder_8     --调用8位加法器声明
port(a8_a,a8_b:in std_logic_vector(7 downto 0);
          a8_s:out std_logic_vector(7 downto 0);
        a8_out:out std_logic);
end component;

component reg_8     --调用8位寄存器声明
port(r8_clk,clr,r8_load:in std_logic;
       r8_in:in std_logic_vector(7 downto 0);
       r8_out:out std_logic);
end component;

component reg_16    --调用16位寄存器声明
port(r16_clk,clr,r16_clr:in std_logic;
           r16_in:in std_logic_vector(8 downto 0);
           cout:out std_logic;
           r16_out:out std_logic_vector(15 downto 0));
end component;
signal q_a,cout:std_logic; 
signal andsd,a,b,aa,bb:std_logic_vector(7 downto 0);
signal dtbin:std_logic_vector(8 downto 0);
signal dtbout:std_logic_vector(15 downto 0);
begin 
  aa<=out_a1&out_a0;
  bb<=out_b1&out_b0;
u1:cnt10           --例化语句
   port map(clk_a1,clr,out_a1);
u2:cnt10
   port map(clk_a0,clr,out_a0);
u3:cnt10          
   port map(clk_b1,clr,out_b1);
u4:cnt10
   port map(clk_b0,clr,out_b0);
u5:BCD_B          
   port map(aa,a);
u6:BCD_B
   port map(bb,b);
u7:reg_8           
   port map(clk,clr,start,a,q_a);
u8:multi_1
   port map(q_a,b,andsd);
u9:adder_8
  port map(dtbout(15 downto 8),andsd,dtbin(7 downto 0),dtbin(8));
u10:reg_16
  port map(clk,clr,start,dtbin,cout,dtbout);
u11:B_BCD          
   port map(clk,cout,dtbout,result);
end arc_multi_8x8;