adder_8.vhd

来自「8位十进制乘法器」· VHDL 代码 · 共 18 行

library ieee;   --8位加法器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
    entity adder_8 is      
        port(a8_a,a8_b:in std_logic_vector(7 downto 0);
                  a8_s:out std_logic_vector(7 downto 0);
                a8_out:out std_logic);
   end adder_8;
  architecture arc_adder_8 of adder_8 is   
         signal ss:std_logic_vector(8 downto 0);  
      signal aa,bb:std_logic_vector(8 downto 0);
  begin
      aa<='0'&a8_a;    bb<='0'&a8_b;     ss<=aa+bb; 
      a8_s<=ss(7 downto 0);   
      a8_out<=ss(8);   
  end arc_adder_8;