reg_8.tan.rpt

8位十进制乘法器

; N/A   ; None         ; 1.500 ns   ; r8_load  ; reg8[1] ; r8_clk   ;
; N/A   ; None         ; 1.500 ns   ; r8_load  ; reg8[2] ; r8_clk   ;
; N/A   ; None         ; 1.500 ns   ; r8_load  ; reg8[3] ; r8_clk   ;
; N/A   ; None         ; 1.500 ns   ; r8_load  ; reg8[4] ; r8_clk   ;
; N/A   ; None         ; 1.500 ns   ; r8_load  ; reg8[5] ; r8_clk   ;
; N/A   ; None         ; 1.500 ns   ; r8_load  ; reg8[6] ; r8_clk   ;
+-------+--------------+------------+----------+---------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+---------+--------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To     ; From Clock ;
+-------+--------------+------------+---------+--------+------------+
; N/A   ; None         ; 10.600 ns  ; reg8[0] ; r8_out ; r8_clk     ;
+-------+--------------+------------+---------+--------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+----------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From     ; To      ; To Clock ;
+---------------+-------------+-----------+----------+---------+----------+
; N/A           ; None        ; 0.400 ns  ; r8_load  ; reg8[0] ; r8_clk   ;
; N/A           ; None        ; 0.400 ns  ; r8_load  ; reg8[1] ; r8_clk   ;
; N/A           ; None        ; 0.400 ns  ; r8_load  ; reg8[2] ; r8_clk   ;
; N/A           ; None        ; 0.400 ns  ; r8_load  ; reg8[3] ; r8_clk   ;
; N/A           ; None        ; 0.400 ns  ; r8_load  ; reg8[4] ; r8_clk   ;
; N/A           ; None        ; 0.400 ns  ; r8_load  ; reg8[5] ; r8_clk   ;
; N/A           ; None        ; 0.400 ns  ; r8_load  ; reg8[6] ; r8_clk   ;
; N/A           ; None        ; 0.200 ns  ; r8_in[2] ; reg8[2] ; r8_clk   ;
; N/A           ; None        ; 0.200 ns  ; r8_in[1] ; reg8[1] ; r8_clk   ;
; N/A           ; None        ; 0.200 ns  ; r8_in[0] ; reg8[0] ; r8_clk   ;
; N/A           ; None        ; 0.200 ns  ; r8_load  ; reg8[7] ; r8_clk   ;
; N/A           ; None        ; -3.900 ns ; r8_in[5] ; reg8[5] ; r8_clk   ;
; N/A           ; None        ; -4.300 ns ; r8_in[7] ; reg8[7] ; r8_clk   ;
; N/A           ; None        ; -4.600 ns ; r8_in[6] ; reg8[6] ; r8_clk   ;
; N/A           ; None        ; -4.600 ns ; r8_in[4] ; reg8[4] ; r8_clk   ;
; N/A           ; None        ; -4.600 ns ; r8_in[3] ; reg8[3] ; r8_clk   ;
+---------------+-------------+-----------+----------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Dec 19 15:45:56 2012
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off reg_8 -c reg_8
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "r8_clk" is an undefined clock
Info: Clock "r8_clk" Internal fmax is restricted to 200.0 MHz between source register "reg8[7]" and destination register "reg8[6]"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A21; Fanout = 1; REG Node = 'reg8[7]'
            Info: 2: + IC(0.300 ns) + CELL(1.000 ns) = 1.300 ns; Loc. = LC6_A21; Fanout = 1; REG Node = 'reg8[6]'
            Info: Total cell delay = 1.000 ns ( 76.92 % )
            Info: Total interconnect delay = 0.300 ns ( 23.08 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "r8_clk" to destination register is 2.400 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'r8_clk'
                Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_A21; Fanout = 1; REG Node = 'reg8[6]'
                Info: Total cell delay = 2.000 ns ( 83.33 % )
                Info: Total interconnect delay = 0.400 ns ( 16.67 % )
            Info: - Longest clock path from clock "r8_clk" to source register is 2.400 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'r8_clk'
                Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC8_A21; Fanout = 1; REG Node = 'reg8[7]'
                Info: Total cell delay = 2.000 ns ( 83.33 % )
                Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: + Micro clock to output delay of source is 0.500 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "reg8[6]" (data pin = "r8_in[6]", clock pin = "r8_clk") is 6.500 ns
    Info: + Longest pin to register delay is 8.300 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_101; Fanout = 1; PIN Node = 'r8_in[6]'
        Info: 2: + IC(2.400 ns) + CELL(1.000 ns) = 8.300 ns; Loc. = LC6_A21; Fanout = 1; REG Node = 'reg8[6]'
        Info: Total cell delay = 5.900 ns ( 71.08 % )
        Info: Total interconnect delay = 2.400 ns ( 28.92 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "r8_clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'r8_clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_A21; Fanout = 1; REG Node = 'reg8[6]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: tco from clock "r8_clk" to destination pin "r8_out" through register "reg8[0]" is 10.600 ns
    Info: + Longest clock path from clock "r8_clk" to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'r8_clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_A21; Fanout = 1; REG Node = 'reg8[0]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 7.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A21; Fanout = 1; REG Node = 'reg8[0]'
        Info: 2: + IC(1.400 ns) + CELL(6.300 ns) = 7.700 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'r8_out'
        Info: Total cell delay = 6.300 ns ( 81.82 % )
        Info: Total interconnect delay = 1.400 ns ( 18.18 % )
Info: th for register "reg8[0]" (data pin = "r8_load", clock pin = "r8_clk") is 0.400 ns
    Info: + Longest clock path from clock "r8_clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'r8_clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_A21; Fanout = 1; REG Node = 'reg8[0]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 3.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 8; PIN Node = 'r8_load'
        Info: 2: + IC(0.500 ns) + CELL(0.800 ns) = 3.300 ns; Loc. = LC7_A21; Fanout = 1; REG Node = 'reg8[0]'
        Info: Total cell delay = 2.800 ns ( 84.85 % )
        Info: Total interconnect delay = 0.500 ns ( 15.15 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Dec 19 15:45:57 2012
    Info: Elapsed time: 00:00:02