reg_8.vhd

8位十进制乘法器

library ieee;   ---8位移位寄存器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity reg_8 is        
port(r8_clk,clr,r8_load:in std_logic;
       r8_in:in std_logic_vector(7 downto 0);
       r8_out:out std_logic);
end reg_8;
architecture arc_reg_8 of reg_8 is     
  signal reg8:std_logic_vector(7 downto 0);  
begin 
  process(r8_clk,clr,r8_load)
    begin
      if clr='1'then 
         reg8<="00000000";
       elsif r8_clk'event and r8_clk='1' then   
         if r8_load='1' then        
            reg8<=r8_in;
         else 
            reg8(6 downto 0)<=reg8(7 downto 1); 
          end if;
       end if;
  end process;
  r8_out<=reg8(0);     
end arc_reg_8;