📄 simim_dtc.mdl
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DstBlock "Add"
DstPort 3
}
Branch {
DstBlock "Add1"
DstPort 3
}
}
}
Line {
SrcBlock "Divide2"
SrcPort 1
Points [50, 0; 0, 10]
DstBlock "Add2"
DstPort 3
}
Line {
SrcBlock "Divide1"
SrcPort 1
Points [115, 0]
DstBlock "Add1"
DstPort 2
}
Line {
SrcBlock "UDC"
SrcPort 1
DstBlock "Gain"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [10, 0; 0, 90]
Branch {
DstBlock "Divide3"
DstPort 1
}
Branch {
Points [0, 165]
Branch {
DstBlock "Divide4"
DstPort 1
}
Branch {
Points [0, 190]
DstBlock "Divide5"
DstPort 1
}
}
}
Line {
SrcBlock "Add"
SrcPort 1
Points [35, 0; 0, 10]
DstBlock "Divide3"
DstPort 2
}
Line {
SrcBlock "Add1"
SrcPort 1
Points [75, 0]
DstBlock "Divide4"
DstPort 2
}
Line {
SrcBlock "Add2"
SrcPort 1
Points [40, 0; 0, 30]
DstBlock "Divide5"
DstPort 2
}
Line {
SrcBlock "Divide5"
SrcPort 1
Points [5, 0; 0, 5]
DstBlock "UC"
DstPort 1
}
Line {
SrcBlock "Divide4"
SrcPort 1
Points [10, 0; 0, 10]
DstBlock "UB"
DstPort 1
}
Line {
SrcBlock "Divide3"
SrcPort 1
Points [0, 0]
DstBlock "UA"
DstPort 1
}
Line {
SrcBlock "sabc"
SrcPort 1
DstBlock "Demux1"
DstPort 1
}
}
}
Block {
BlockType Reference
Name "Universal Bridge"
Ports [1, 0, 0, 0, 0, 3, 2]
Position [195, 122, 250, 198]
Orientation "left"
SourceBlock "powerlib/Power\nElectronics/Universal Bridge"
SourceType "Universal Bridge"
ShowPortLabels on
Arms "3"
SnubberResistance "1e5"
SnubberCapacitance "inf"
Device "MOSFET / Diodes"
Ron "1e-3"
Lon "0"
ForwardVoltages "[ 0 0 ]"
ForwardVoltage "0"
GTOparameters "[ 10e-6 , 20e-6 ]"
IGBTparameters "[ 1e-6 , 2e-6 ]"
Measurements "None"
}
Block {
BlockType Constant
Name "W"
Position [415, 260, 445, 290]
NamePlacement "alternate"
Value "100"
}
Block {
BlockType Reference
Name "XY Graph"
Ports [2]
Position [755, 588, 785, 632]
SourceBlock "simulink/Sinks/XY Graph"
SourceType "XY scope."
ShowPortLabels on
xmin "-1.1"
xmax "1.1"
ymin "-1.1"
ymax "1.1"
st "-1"
}
Block {
BlockType SubSystem
Name "psy"
Ports [1, 2]
Position [535, 515, 625, 590]
Orientation "left"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "psy"
Location [0, 82, 1268, 999]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "psy_albe"
Position [75, 243, 105, 257]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 2]
Position [135, 229, 140, 271]
BackgroundColor "black"
ShowName off
Outputs "2"
DisplayOption "bar"
}
Block {
BlockType Fcn
Name "Fcn"
Position [305, 145, 365, 175]
Expr "sqrt(u(1)^2+u(2)^2)"
}
Block {
BlockType SubSystem
Name "ang_calculate"
Ports [2, 1]
Position [300, 229, 400, 271]
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "ang_calculate"
Location [6, 82, 1274, 969]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "flinkag_a"
Position [80, 188, 110, 202]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "flinkag_b"
Position [80, 153, 110, 167]
Port "2"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Constant
Name "Constant"
Position [350, 155, 380, 185]
Value "3.1415926"
}
Block {
BlockType Product
Name "Divide"
Ports [2, 1]
Position [150, 143, 170, 212]
Inputs "*/"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
OutScaling "2^-10"
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Fcn
Name "Fcn1"
Position [240, 130, 300, 160]
Expr "atan(u)"
}
Block {
BlockType Fcn
Name "Fcn2"
Position [245, 190, 305, 220]
Expr "atan(u)"
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [395, 195, 415, 215]
ShowName off
IconShape "round"
Inputs "++|"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Switch
Name "Switch"
Position [490, 132, 515, 218]
InputSameDT off
SaturateOnIntegerOverflow off
}
Block {
BlockType Outport
Name "angle"
Position [565, 168, 595, 182]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "flinkag_b"
SrcPort 1
DstBlock "Divide"
DstPort 1
}
Line {
SrcBlock "flinkag_a"
SrcPort 1
Points [15, 0]
Branch {
DstBlock "Divide"
DstPort 2
}
Branch {
Points [0, 80; 315, 0; 0, -100]
DstBlock "Switch"
DstPort 2
}
}
Line {
SrcBlock "Divide"
SrcPort 1
Points [25, 0]
Branch {
Points [0, -35]
DstBlock "Fcn1"
DstPort 1
}
Branch {
Points [0, 25]
DstBlock "Fcn2"
DstPort 1
}
}
Line {
SrcBlock "Fcn1"
SrcPort 1
DstBlock "Switch"
DstPort 1
}
Line {
SrcBlock "Constant"
SrcPort 1
Points [20, 0]
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Fcn2"
SrcPort 1
DstBlock "Sum"
DstPort 2
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Switch"
DstPort 3
}
Line {
SrcBlock "Switch"
SrcPort 1
DstBlock "angle"
DstPort 1
}
}
}
Block {
BlockType MATLABFcn
Name "sector_judg"
Position [450, 235, 510, 265]
MATLABFcn "sector(u)"
}
Block {
BlockType Outport
Name "sector"
Position [560, 243, 590, 257]
IconDisplay "Port number"
BusOutputAsStruct off
}
Block {
BlockType Outport
Name "psy"
Position [555, 153, 585, 167]
Port "2"
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "ang_calculate"
SrcPort 1
Points [0, 0]
DstBlock "sector_judg"
DstPort 1
}
Line {
SrcBlock "sector_judg"
SrcPort 1
Points [0, 0]
DstBlock "sector"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 1
DstBlock "ang_calculate"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 2
DstBlock "ang_calculate"
DstPort 2
}
Line {
SrcBlock "psy_albe"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "Demux"
DstPort 1
}
Branch {
Points [0, -90]
DstBlock "Fcn"
DstPort 1
}
}
Line {
SrcBlock "Fcn"
SrcPort 1
DstBlock "psy"
DstPort 1
}
}
}
Block {
BlockType Constant
Name "psy*"
Position [400, 650, 430, 680]
NamePlacement "alternate"
}
Block {
BlockType SubSystem
Name "switchtable*"
Ports [3, 7]
Position [215, 422, 325, 598]
Orientation "left"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "switchtable*"
Location [2, 82, 1270, 977]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "dT"
Position [75, 378, 105, 392]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "sector"
Position [140, 323, 170, 337]
Port "2"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "dPsy"
Position [155, 398, 185, 412]
Port "3"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType DataTypeConversion
Name "Data Type Conversion"
Position [750, 453, 825, 487]
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType DataTypeConversion
Name "Data Type Conversion1"
Position [750, 523, 825, 557]
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType DataTypeConversion
Name "Data Type Conversion2"
Position [750, 593, 825, 627]
RndMeth "Floor"
SaturateOnIntegerOverflow off
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 3]
Position [735, 287, 740, 393]
BackgroundColor "black"
ShowName off
Outputs "3"
DisplayOption "bar"
}
Block {
BlockType Demux
Name "Demux1"
Ports [1, 3]
Position [660, 434, 665, 646]
BackgroundColor "black"
ShowName off
Outputs "3"
DisplayOption "bar"
}
Block {
BlockType Fcn
Name "Fcn"
Position [270, 380, 330, 410]
Expr "u(1)+u(2)*2+1"
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [1, 1]
Position [690, 454, 720, 486]
Operator "NOT"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Logic
Name "Logical⌨️ 快捷键说明
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