sja1000.h

ATMEGA128 对 SJA1000 寄存器读写

/* sja1000.h
 * Header file for the mege0 driver.
 * Written by lmj
 * Version 0.1  24 May 2008
 */

/*
*******************************************************************
* 1. SJA1000 的主要新功能
* 2. 标准帧和扩展帧信息的接收和传送
* 3. 接收FIFO 64 字节
* 4. 在标准和扩展格式中都有单/双验收滤波器含屏蔽和代码寄存器
* 5. 读/写访问的错误计数器
* 6. 可编程的错误限制报警
* 7. 最近一次的误码寄存器
* 8. 对每一个CAN 总线错误的错误中断
* 9. 仲裁丢失中断以及详细的位位置
* 10. 一次性发送当错误或仲裁丢失时不重发
* 11. 只听模式CAN 总线监听无应答无错误标志
* 12. 支持热插无干扰软件驱动位速检测
* 13. 硬件禁止CLKOUT 输出
********************************************************************
*/

#ifndef _sja1000_h
#define _sja1000_h

#define SJA1000_IRQ	0x04
#define SJA1000_CS	(1 << 2)
#define SJA1000_ALE	(1 << 2)
#define SJA1000_RD	(1 << 1)
#define SJA1000_WR	(1 << 0)

//void sja1000_rx_int(void);

/* PeliCAN  mode (extend) */
#define SJA_MOD		0		// Mode register
#define SJA_CMR		1		// Command register
#define SJA_SR		2		// Status register
#define SJA_IR		3		// Interrupt register
#define SJA_IER		4		// Interrupt Enable
#define RESERVED1	
#define SJA_BTR0	6		// Bus Timing register 0
#define SJA_BTR1	7		// Bus Timing register 1
#define SJA_OCR		8		// Output Control register
#define SJA_TST		9		// Test register(for test only)
#define RESERVED2
#define SJA_ALC		11		// Arbitration Lost Capture
#define SJA_ECC		12		// Error Code Capture
#define SJA_EWLR	13		// Error Warning Limit
#define SJA_RXERR	14		// RX Error Counter
#define SJA_TXERR	15		// TX Error Counter
#define SJA_RST_ACCODE	16	//!!! Acceptance code ,for 4 bytes addr16--addr19
#define SJA_RXB		16
#define SJA_FRAME	16		// Frame information
#define SJA_MSGID	17		//!!! Message identifer ,for 4 bytes addr17--addr20
#define SJA_DATA_SFF	19
#define SJA_RST_ACMASK	20	//!!! Acceptance mask ,for 4 bytes addr20--addr23
#define SJA_DATA_EFF	21	//!!! Extend received/transmit data 1
				// for 8 bytes addr21--addr28
#define SJA_FIFO_SFF	27	// FIFO position register in sff mode
#define SJA_RMC		29		// Receive message counter
				// (address of current MSG)
#define SJA_RBSA	30		// Receive Buffer Start Addr. 
#define SJA_CDR		31		// Clock Divider
#define SJA_RAM		32		// sja1000' internal ram address
#define SJA_FIFO	32		// 32- 95 64 bytes:fifo address space
#define SJA_TXB		96		// 96 - 108 13 bytes:tx buffer address  space
				/* 109 - 127 not used? */


/* SJA_MOD */
#define SJA_MOD_RST	(1 << 0)	/* reset mode control */
#define SJA_MOD_LO	1	/* listen only control */
#define SJA_MOD_ST	2	/* self test control */
#define SJA_MOD_AF	3	/* acceptance filter:1->single filter: 0->double */
#define SJA_MOD_SE	4	/* set to sleep mode */

/* SJA_CMR */
#define SJA_CMR_TR	0	/* transmit request */
#define SJA_CMR_AT	1	/* abort transmit */
#define SJA_CMR_RRB	2	/* release receive fifo buffer */
#define SJA_CMR_CDO	3	/* clear data overflow bit */
#define SJA_CMR_SRR	4	/* self receive reques, make a loop test? */

/* SJA_SR */
#define SJA_SR_BS	7	/* bus shutdown */
#define SJA_SR_ES	6	/* error status */
#define SJA_SR_TS	5	/* transmit status; indicat it's transmitting */
#define SJA_SR_RS	4	/* receive status; indicat it's receiving */
#define SJA_SR_TCS	3	/* transmit complete status; indicat last trasmit complete */
#define SJA_SR_TBS	2	/* transmit buffer status; be ready for cpu's writing */
#define SJA_SR_DOS	1	/* data overflow status; rxfifo overflow,and lost some data */
				/* when occur data overflow, it will drop the new message  */
				/* but override the old one */
#define SJA_SR_RBS	0	/* receive buffer status, 1 -> has message */
				/* but how many messages? */

/* SJA_IR */
				/* all the following bits are valid when the */
				/* correlative interrupt enable bit been set */
#define SJA_IR_BEI	7	/* bus error interrupt */
#define SJA_IR_ALI	6	/* arbitration lost interrupt */
#define SJA_IR_EPI	5	/* error passive interrupt, when error counter */ 
				/* over 127 or error status reactive */
#define SJA_IR_WUI	4	/* wakeup interrupt,occurs when sleep and detect bus action */ 
#define SJA_IR_DOI	3	/* data overflow interrupt */ 
#define SJA_IR_EI	2	/* error interrupt;set when error status bit */
				/* or bus status bit changed */ 
#define SJA_IR_TI	1	/* transmit interrupt;set when tranmit status bit set */
#define SJA_IR_RI	0	/* receive interrupt;set when rxfifo not empty */

/* SJA_IER */
#define SJA_IR_BEIE	(1 << 7)	/* all relate to SJA_IR's correlation bit */
#define SJA_IR_ALIE	(1 << 6)
#define SJA_IR_EPIE	(1 << 5)
#define SJA_IR_WUIE	(1 << 4)
#define SJA_IR_DOIE	(1 << 3)
#define SJA_IR_EIE	(1 << 2)
#define SJA_IR_TIE	(1 << 1)
#define SJA_IR_RIE	(1 << 0)

/* SJA_BTR0 */
/* Fcan = Fxtal / (2 * (SJA_BTR0 & SJA_BTR0_BRP_MSK)) */
#define SJA_BTR0_BRP_MSK	0x3f	/* bauld rate prevalue */

/* Tsjw = Tcan * (SJA_BTR0_SJW_MSK & SJA_BTR0) */
#define SJA_BTR0_SJW_MSK	0xc0	/* msb 2 bits */
				
/* SJA_BTR1 */
#define SJA_BTR1_SAM	7	/* sample frequency 1 for 3 times, 0 for one time */

/*  位周期 =  tSYNCSEG + tTSEG2 + tTSEG1 */
/* tSYNCSEG = 1 tSCL 同步段时间*/
/* tTSEG2 = tSCL *((SJA_BTR1_TSEG2_MSK & SJA_BTR1) + 1) 第二段时间 */
#define SJA_BTR1_TSEG2_MSK	0x30

/* tTSEG1 = tSCL *((SJA_BTR1_TSEG1_MSK & SJA_BTR1) + 1) 第一段时间 */
#define SJA_BTR1_TSEG1_MSK	0x0f

/* SJA_OCR */
#define SJA_OCR_OCTP1	7
#define SJA_OCR_OCTN1	6
#define SJA_OCR_OCPOL1	5
#define SJA_OCR_OCTP0	4
#define SJA_OCR_OCTN0	3
#define SJA_OCR_OCPOL0	2
#define SJA_OCR_OCMODE1	1
#define SJA_OCR_OCMODE0	0

/* SJA_ALC */
/* Arbitration Lost Capture, record the bit where lost the arbitration */

/* SJA_ECC */
				/* error code capture register */
#define SJA_ECC_ERRC_MSK	0xc0
#define SJA_ECC_DIR	5	/* direction: 1->rx error: 0->tx error */
#define SJA_ECC_SEG	0x1f	/* low 5 bits valid */

/* SJA_EWLR */

/* SJA_RXERR */

/* SJA_TXERR */

/* SJA_RMC */
#define SJA_RMC_MSK	0x1f	/* low 5 bits valid */

/* SJA_RBSA */
#define SJA_RBSA_MSK	0x3f	/* low 6 bits valid */	

/* SJA_CDR */
#define SJA_CDR_CLKOUT_MSK	0x07
#define SJA_CDR_CANMOD	7	/* 1->peliCAN 0->BasicCan */
#define SJA_CDR_CBP	6
#define SJA_CDR_RXINTEN	5	/* use tx1 as a dedicate receive interrupt line */
#define SJA_CDR_CLKOFF	3


// void sja1000_init (void);

void sja100_rw_test(void);

#endif	/* _sja1000_h */